Seu and Sefi error detection and correction on a ddr3 memory system

• Autores: Ana Cóbreces, Alberto Regadío Carretero, Jesús Tabero Godino, Pedro Reviriego Vasallo, Alfonso Sánchez-Macián, Juan Antonio Maestro
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 91-1, 2018, págs. 23-30
• Idioma: inglés
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• Resumen

  • This paper presents an embedded design that performs a novel Single Event Upset (SEU) and Single Event Functional Interrupt (SEFI) detection and recovery technique for DDR3 Synchronous Dynamic Random-Memories (SDRAM) memories in space applications. Using a memory system composed of four devices, this SEFI recovery method allows to restore the content of one entire device using the data and the Error Correction Code (ECC) bits stored in the other three devices. This design is implemented on a Xilinx Zynq-7000 System on Chip (SoC). The SEU detection and the recovery functionality is implemented on a Xilinx Zynq as an AXI bus peripheral. This peripheral is connected with the Processing System (PS) of the device via AXI bus, where a SEFI detection algorithm is implemented in a software application that runs in the ARM Cortex-A9. The developed technique also allows to inject errors to test the whole functionality.