Analysis of the degradation mechanisms occurring in the topside interconnections of IGBT power devices during power cycling

• Autores: N. Dornic, A. Ibrahim, Z. Khatir, S.H. Tran, J.P. Ousten, J. Ewanchuk, S. Mollov
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 88-90, 2018, págs. 462-469
• Idioma: inglés
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• Resumen

  • This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on Semikron SKIM 63 power modules, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analysis. Four-probe measurements are implemented on the chips so that the evolution of physical parameters representative of the degradation in the metallization and the bond wire contacts can be obtained. Finally, optical microscopy analysis of cross-sections at the wire bond contact interface is carried out to corroborate the electrical measurements to the crack length growth after specific aging intervals.