Failure analysis on 14 nm FinFET devices with ESD CDM failure

• Autores: C. Shaalini, P. K. Tan, Y.Z. Zhao, B.H. Liu, Y.Z. Ma, A. Quah, Y.-L. Pan, J.B.H. Tan, Z.H. Mai
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 88-90, 2018, págs. 321-333
• Idioma: inglés
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• Resumen

  • Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14 nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. In most ESD failure FA, most of the time found Electrical Over Stress (EOS), the important is to understand which process layer or design causing the EOS. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14 nm FinFET FA by old technology node FA equipment, and the FA findings. Finally, the ESD failure was identified with Scanning Transmission Electron Microscope (STEM)/Energy Dispersive Spectroscopy (EDS) analysis. The FA findings of the failure are related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.