Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

• Autores: Alexis Ramos, Juan Antonio Maestro, Pedro Reviriego Vasallo
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 78, 2017, págs. 205-211
• Idioma: inglés
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• Resumen

  • Abstract The reliability of microprocessors is a big concern in space environments, where they are exposed to cosmic radiation. This radiation can produce Single Event Upsets (SEUs). Some of these microprocessors, often called soft processors, are implemented on SRAM-based FPGAs instead of being manufactured as an ASIC. Fault injection campaigns are needed in order to estimate the soft processor reliability in this harsh environment. This work, characterizes a new RISC soft-core, called lowRISC, based on the RISC-V ISA. Ten tests have been carried out to characterize the SEU sensitivity of lowRISC. Also, we have performed a comparison among lowRISC and other microprocessors, concluding that their sensitivities are all in the same range.