Journal of electronic testing: Theory and applications

• 

  Año 2004, Número 5

  • Editorial

    V. D. Agrawal

    pág. 459

    

  • Test Technology Technical Council Newsletter

    P. Prinetto

    págs. 461-462

    

  • Guest Editorial

    C. Metra, M. S. Reorda

    pág. 463

    

  • Design of Embedded Self-Testing Checkers for t-UED and BUED Codes

    S. Tarnick

    págs. 465-477

    

  • An Analog Checker with Input-Relative Tolerance for Duplicate Signals

    H. G. Stratigopoulos

    págs. 479-488

    

  • Efficient Realization of Parity Prediction Functions in FPGAs

    H. S. Kim, J. C. Lo

    págs. 489-499

    

  • Model for Transient Fault Susceptibility of Combinational Circuits

    D. Rossi, C. Metra, M. Omana

    págs. 501-509

    

  • A New Approach to the Analysis of Single Event Transients in VLSI Circuits

    M. S. Reorda, M. Violante

    págs. 511-521

    

  • A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

    S. Matakias, A. Arapoyanni, T. Haniotakis, Y. Tsiatouhas

    págs. 523-531

    

  • IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors

    A. K. Nieuwland, R. P. Kleihorst

    págs. 533-542

    

  • A Two-Level Power-Grid Model for Transient Current Testing Evaluation

    Jaume Agapit Segura Fuster, Bartomeu Alorda Ladaria, Vicente José Canals Guinand

    págs. 543-552

    

  • Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features

    S. G. Miremadi, M. Mohandespour, A. Rajabzadeh

    págs. 553-567