Journal of electronic testing: Theory and applications

• 

  Año 2005, Número 4

  • Editorial

    E. I. Vishwani D. Agrawal

    pág. 343

    

  • Test Technology Newsletter

    E. Bruce Kim

    pág. 345

    

  • Guest Editorial

    R. G. Cecilia Metra

    pág. 347

    

  • Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip

    D. Barros Júnior, Marcial Jesús Rodriguez Irago

    págs. 349-363

    

  • Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation

    R. Leveugle, A. Ammari, K. Hadjiat

    págs. 365-376

    

  • Self-Checking Voter for High Speed TMR Systems

    J. M. Cazeaux

    págs. 377-389

    

  • Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codesâ¿¿

    S. Tarnick

    págs. 391-404

    

  • The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit

    R. Cutajar, A. Richardson, C. Jeffrey

    págs. 405-416

    

  • Low Cost On-Line Testing Strategy for RF Circuits

    M. Negreiros

    págs. 417-427

    

  • A Comparative Evaluation of Designs for Reliable Memory Systems

    G. C. Cardarilli

    págs. 429-444

    

  • Memory Defect Tolerance Architectures for Nanotechnologies

    M. Nicolaidis

    págs. 445-455