Design and implementation of embedded face detection systems: (diseño e implementación de sistemas empotrados de detección de caras)
- Autores: Laurentiu Acasandrei
- Directores de la Tesis: Ángel Barriga Barros (dir. tes.)
- Lectura: En la Universidad de Sevilla ( España ) en 2014
- Idioma: español
- Tribunal Calificador de la Tesis: Luis Miguel Bergasa Pascual (presid.), Rafael Domínguez Castro (secret.), Richard Kleihorst (voc.), Enrique Cabello Pardos (voc.), Santiago Sánchez Solano (voc.)
- Menciones:
- Europea
- Calificación: Sobresaliente Cum Laude
- Materias:
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- Resumen
In recent years a new field has emerged: Embedded Vision . This designation refers to machines that understand their environment through visual means. Embedded Vision is the merging of two fields: embedded systems and computer vision. By their definition an embedded system is any microprocessor-based system that isn¿t a general-purpose computer. The primary goal of the entities (research institutes or companies) involved with Embedded Vision is to incorporate computer vision capabilities (i.e. algorithms) into low-cost, energy-efficient embedded system. All the work presented in this Thesis fits perfectly to the Em-bedded Vision field. Two important object detection algorithm, i.e. Viola-Jones and Local Binary Patterns, were ported to a generic embedded system, had their performance bottlenecks analyzed and software and algorithmic optimization solutions were proposed. To make the detection embedded systems faster and more energy efficient, hardware accelerators were designed for the Viola-Jones and Local Binary Patterns algorithms. A Software-Hardware co-design methodology is proposed, that guides the designer during the complex process of embedded algorithm porting, performance analysis, bottlenecks identification, software and hardware partitioning of the embedded system. For the image processing algorithms that need a large bandwidth, the critical importance of the communication architecture is acknowledged and for the AMBA buses (APB, AHB, AXI, AXI-Stream) master and slaves interfaces were designed. Targeting very lower applications the Viola-Jones hardware accelerator IP was implemented in ASIC. Due to technological incompatibilities, pin and area constraints, several important units of the IP needed redesign. As a result of the redesign process three arithmetical circuit generators (a custom signed/unsigned combinational multiplier, a Nonrestoring pipeline square root and RADIX 4 sequential square root) were implemented. In this section is presented in detail for each chapter the main contributions.
Chapter 1 Main Contributions ¿ Face detection plays a very important role in biometrics and a small revision of the most used techniques has been made.
¿ For the two most known face detection algorithms, i.e. Viola-Jones and Local Binary Patterns (LBP), it was presented the two common elements: the Integral Image used in fast feature extraction and the AdaBoost mechanism used for training of the cascaded classifier.
¿ It was proposed a four stage Software-Hardware co-design methodology that was used in designing Viola-Jones and LBP based face detection embedded systems.
Chapter 2 Main Contributions ¿ In this chapter it was presented the characteristics of LEON3 processor design environment and the hardware host: the Xilinx ML505 development board. The combination of open source LEON3 softcore processor and XILINX ML505 resulted in a very flexible framework for Hardware-Software co-design, ideal for developing image processing applications.
Chapter 3 Main Contributions ¿ In this chapter we made a brief introduction into the design challenges of the communication architectures and their impact on the system performance.
¿ It is followed by an overview of past and current communication architectures.
¿ A presentation of generic elements, mechanisms, bus protocols and topologies common to most of the communication architectures, is made.
¿ For the AMBA communication standard, masters and slave interfaces (APB, AHB, AXI, AXI-Stream) were designed. These interfaces can be employed in a large variety design constraints and systems (i.e. for low power, low speed up to high speed streaming applications).
¿ For the APB slave and AHB master/slave interfaces a design and test framework, based on GRLIB library, is provided. Unfortunately, due to limitation imposed by license of every industry/academic AXI bus functional models, for the AXI and AXI-Stream no test framework is provided.
¿ The APB, AHB, AXI, AXI-Stream master and slave interfaces are technology independent and they are released as an open source hardware IP described in data flow VHDL.
Chapter 4 Main Contributions ¿ The LBP algorithm for object detection, with emphasis of face detection, is described.
¿ Porting OpenCV baseline LBP face detection application to a generic embedded system.
¿ In depth analysis of the performance of the MB-LBP face detection software embedded implementation. The performance of the embedded software was measured and the most important design challenges were emphasized.
¿ For the detection algorithms, besides frames per second, new performances metrics were introduced: number of search windows per image and bandwidth data usage. ¿ Instead of using the standard Integral representation we propose a Confined Integral representation that reduces the memory footprint and bandwidth by half.
¿ The software and algorithm improvement were not sufficiently fast for a real time face detection application. An AMBA compliant, multi-core LBP hardware accelerator was designed to speed up the detection.
¿ The resulted embedded face detection system is time deterministic and uses a customizable AMBA IP hardware accelerator. The IP can be used as universal accelerator for MB LBP based applications. The IP is modularized, highly configurable and technology independent.
¿ The embedded implementation acceleration gain is between 5 to 8 times, while the hardware LBP feature evaluation gain is between 69 and 139 times.
¿ The ported and embedded software LBP implementations, the complete LBP face detection embedded system and the multi-core LBP hardware accelerator IP are available as open source resources.
Chapter 5 Main Contributions ¿ The Viola-Jones algorithm for object detection, with emphasis of face detection, is described.
¿ Porting the OpenCV Viola-Jones face detection application to a generic embedded environment.
¿ Analyzing the performance bottlenecks and optimizing the ported embedded face detection software application.
¿ An optimized Viola-Jones object detection algorithm is proposed. The optimization changes are subtle and they do not affect the accuracy of the algorithm but the detection speed is increased by 3 times.
¿ A three times acceleration for the algorithm running on low power, low frequency embedded system is not sufficiently fast for a real time face detection application. Instead a Software-Hardware embedded co-design paradigm was used and a dedicated face detection hardware accelerator IP, that can speed-up the detection by a factor of 10-12 times, is proposed. The face detection hardware accelerator IP is built on the principle of resource sharing, i.e. when the system is performing different tasks than face detection, the hardware IP resources (on-chip shared memory, multiplier and integer squared root unit) can be used freely by the system. The IP is modularized, highly configurable and technology independent.
¿ The ported and embedded software Viola-Jones implementations, the complete Viola-Jones face detection embedded system and the Viola-Jones hardware accelerator IP are available as open source resources.
Chapter 6 Main Contributions ¿ A scalable low area multiplier (SLAM) architecture targeting low power/area applications is proposed. The multiplier module generator is parameterized in terms of input operands width (N). The multiplier module generator consists of synthesizable VHDL code for both signed and unsigned arithmetic circuit. In order to facilitate the verification of the circuit during the simulation the model includes self test validation. The module description is technology independent and can be implemented in FPGA or in a custom ASIC.
¿ Starting from the algorithm description of a RADIX 4 digit recurrence square root, a custom integer RADIX 4 sequential SQR ASIC generator architecture is proposed. An input data scaling and result scaling circuits were added to the architecture in order for the algorithm to work with integer numbers. The RADIX 4 digit recurrence square root algorithm doesn¿t specify the hardware circuits for implementing its inner blocks and depending on the project constraints, the designer was free to choose the appropriate hardware for each inner block. The custom integer RADIX 4 SQR ASIC generator has variable width of input data.
¿ Based on the most popular square root algorithm, i.e. nonrestoring SQR, a custom pipelined, high throughput combinational SQR generator architecture is proposed. Pipelining the rows of the nonrestoring SQR generator, uses a mechanism that, based on the estimation of the critical path between two consecutive pipeline levels, optimally places a new pipeline.
¿ Porting the Viola-Jones Object Detection IP to an ASIC technology, i.e. TMSC 90 nm low power, was a task filled with challenges. The biggest challenges were: reduced number of IO pins, low ASIC area, redesign of arithmetic circuits (multipliers and square root units) for optimal area and power usage and sharing the die area with unrelated IPs that had different constraints and requirements. As a result of the porting process three arithmetical circuit generators (a custom signed/unsigned combinational multiplier, a Nonrestoring pipeline ISQR and RADIX 4 sequential ISQR) were implemented. These generators are described in behavioural hardware descriptive language (HDL) and they are technology independent. The new Viola-Jones Object Detection IP occupies ~ 1mm2, where the Shared Memory takes more that 60% of the IP area. The worst case delay is estimated at 8.66 ns. The characterization and measurements of the ASIC samples, is a pending task for the near future.
¿ This ASIC is intended to be used as a very low lower coprocessor unit inside a object detection system where a host (a microprocessor or a very low power FPGA) controls the detection flow and also acts as an intermediary, i.e. a proxy, between the ASIC and the system memory
