On-chip monitor for mixed-signal testing based on x-y zoning
- Autores: Ricard Sanahuja Moliner
- Directores de la Tesis: Luz Balado (dir. tes.)
- Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2006
- Idioma: español
- Tribunal Calificador de la Tesis: Joan Figueras Pamies (presid.), José Antonio Rubio Solà (secret.), Miquel Roca Adrover (voc.), Joao Paulo Teixeira (voc.), Adoración Rueda Rueda (voc.)
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- Resumen
Test of Integrated Circuits (ICs) is a topic that has been growing in importance in the last decades. Nowadays, about 50% of the total IC cost is related to test. In the past few years, the improvements of microelectronic technology gave the tool to include Analog and Digital structures sharing a unique IC substrate, in what went by the name of Mixed-Signal (M-S) ICs. The continuous variability of analogue signals and the lack of widely accepted fault models in this domain make analogue and M-S Test more demanding and harder than Digital Testing. The analog part of an M-S IC uses to take up little IC area but its test is still one of the challenges for microelectronic designers and researchers.
On the other hand, Automatic Test Equipments (ATEs) require higher bandwidths than the circuit being tested and demand high-speed sampling techniques. In addition, the signal processing is performed off-line and requires extensive resources in Analog-ATE time and memory, while been reduced the accessibility to some internal parts of the chip.
Alternative solutions have been proposed to diminish the AATE cost. Usually the solution comes by moving the test procedure (total or partial) inside the chip. Build In Test (BIT) is a method that weaves most of these problems into a satisfying solution.
In this thesis, a BIT approach is proposed, theoretically studied and validated with simulation and experimental results. The proposal is intended to detect parametric and structural faults in the Circuit Under Test (CUT). From the first electronic devices on, Lissajous curves have been used in electronics to test and tune filters and other resources. In this project, human eye has been substituted by an electronic element able to detect changes in the shape of the orthogonal composition of two electronic signals.
The proposal is based on an X-Y zoning Monitor that uses the CUT's input/Output signals in order to generate a Lissajous composition. The BIT output generates a digital signature which can be internally processed by other embedded structures of the M-S circuit or be externally connected to a digital ATE.
The thesis includes theoretical studies to model and look for the best configuration of the Analog X-Y zoning Monitor. Based on this theory, a first experimental prototype based on programmable analog devices has been developed. Results showed the viability of the method. However, BIT also means minimum IC area, influence of the test on the CUT and other IC related aspects, which need silicon validation. Then, a full-custom IC was designed, based on Floating Gate (FG) and Quasi Floating Gate (QFG) transistors, exhaustively simulated and fabricated in a standard CMOS process.
Extensive experiments demonstrate that FG and QFG implementations worked as expected, according the extracted simulation results and offer a good compromise area-performance. For the CUT&BIT demonstrator cells, Montecarlo simulations have been done to evaluate how process variations affect the CUT&BIT behavior and establish the possible escapes and yield losses. Experimental results, on samples after IC fabrication, show the viability of the integrated Monitor and the X-Y zoning approach.
