High-performance decimal floating point units

• Autores: Álvaro Vázquez Álvarez
• Directores de la Tesis: Elisardo Antelo Suárez (dir. tes.)
• Lectura: En la Universidade de Santiago de Compostela ( España ) en 2009
• Idioma: inglés
• Tribunal Calificador de la Tesis: Emilio López Zapata (presid.), Javier Díaz Bruguera (secret.), Francisco Tirado Fernández (voc.), Paolo Montuschi (voc.), José María Llaberia Griño (voc.)
• Materias:
  • Matemáticas
    • Ciencia de los ordenadores
      • Diseño con ayuda de ordenador
  • Física
    • Electrónica
      • Circuitos integrados
  • Ciencias tecnológicas
    • Tecnología de los ordenadores
      • Arquitectura de ordenadores
      • Diseño lógico
• Enlaces
  • Tesis en acceso abierto en: MINERVA
• Resumen

  • The main subject of this PhD. thesis is the research and development of new algorithms and high-performance hardware architectures for decimal fixed and floating-point arithmetic.

    Current financial, e-commerce and user-oriented applications make an intensive use of integer and fractional numbers represented in decimal radix. This makes an attractive opportunity for the microprocessor manufactures to provide a dedicated DFU (decimal floating-point unit) in their new high-end microprocessors. This interest is supported by the recent approval of the revision of the IEEE 754 floating-point standard (IEEE 754-2008), which incorporates a specification for decimal arithmetic.

    In this context, this Ph.D. thesis presents the research and design of new algorithms and high-performance architectures for DFX (decimal fixed-point) and DFP (decimal floating-point) units to evaluate in hardware the basic arithmetic operations, that is, add/sub, multiplication (and fused multiply-add) and division. The objective is to obtain efficient hardware implementations, being competitive with other proposals from both the academia and the industry. We have studied the use of new algorithms, decimal encodings and methods to improve the performance and efficiency of the resultant architectures. With the applications of these concepts, the resulting units have a reduced latency. Moreover, we have opened new paths that could serve as a design guide design for future commercial processors.

    A further contribution was focused on improving the reliability of computations. We have proposed a new method for sum error checking applied to BCD addition/subtraction, which presents a reduced hardware complexity when compared with other solutions used in current microprocessors.