Energy Efficient and High–Performance FIR Filter Design on Spartan–6 FPGA

• Bishwajeet Pandey ^[1] ; Abhishek Jain ^[1] ; Abhishek Kumar ^[1] ; Pervesh Kumar ^[2] ; Akbar Hussain ^[3] ; Jason Levy ^[4] ; Bhawani Shankar Chowdhry ^[5]
  1. [1] Thapar University

     Thapar University

     India

     
  2. [2] Sungkyunkwan University

     Sungkyunkwan University

     Corea del Sur

     
  3. [3] Aalborg University

     Aalborg University

     Dinamarca

     
  4. [4] University of Hawaii (Estados Unidos)
  5. [5] Mehran University of Science and Technology (Pakistán)

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• Localización: 3c Tecnología: glosas de innovación aplicadas a la pyme, ISSN-e 2254-4143, Vol. 8, Nº. Extra 1, 2019 (Ejemplar dedicado a: “2nd International Multi–Topic Conference on Engineering and Science”), págs. 36-49
• Idioma: inglés
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• Resumen

  • In this paper, we are going to design the energy efficient Gaussian low pass FIR filter on spartan-6 FPGA. To make an energy efficient filter, we have used different methods in this paper like capacitance scaling, frequency scaling, and then we analysed the demand of power by Gaussian low pass FIR filter. The frequency range which is used in this paper is 1 GHz, 2GHz, 2.5GHz, 5 GHz, 10 GHz and the range of capacitance which we have used un this paper is 5pF, 10pF, 25pF, 40pF and 50 pF. An FIR filter always remnants in linear phase with the help of symmetric co-efficient and this is the very useful feature of the FIR filter for phase sensitive application like data communications etc. At present there are many different methods for communications and networking. So, in this paper, we have designed an energy efficient FIR filter and that design will faster than traditional design.