Resumen de A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs
Victor Manuel Gonçalves Martins, Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Marcelo Daniel Berejuck, Eduardo Augusto Bezerra
Dynamic Partial Reconfiguration (DPR) has been used as a solution to deal with permanent faults in space-borne based on off-the-shelf Field Programmable Gate Array (FPGA) devices when they are exposed to the radiation environment. Mechanisms based on DPR must detect the permanent fault in a module and perform the reconfiguration process. A major issue is the amount of silicon resources reserved for that, as the design methodology employed so far requires different partial implementations for the same module. This work proposes a design flow and describes a mechanism to deal with permanent faults, in which the amount of Reconfigurable Partitions (RPs) is reduced, resulting in a better usage of silicon resources available in an FPGA.
