Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits

• Autores: Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 79, 2017, págs. 380-386
• Idioma: inglés
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• Resumen

  • Abstract In three-dimensional integrated circuits (3DICs) aggressive wafer-thinning can lead to large thermal gradients, including spikes in individual device temperatures. In a non-thinned circuit, the large bulk silicon wafer on which devices are built works as a very good thermal conductor, enabling heat to diffuse laterally. In this paper we use measurement and simulation results to examine the normalized temperature rise of an on-chip heater in a two-tier bump-bonded 3D stacked system. We begin by experimentally validating our simulation model and then use it to formulate best and worst case scenarios for the temperature rise in such a system. Die thinning is seen to have a pronounced effect on the thermal response, which can adversely affect system reliability. Thinning the top tier from 725 μm to 10 μm resulted in approximately an 8 times increase in the normalized temperature rise of the heater in our test chip for the worst case scenario and just over a 6 times increase for the best case scenario.