New structure with SiO2-gate-dielectric select gates in vertical-channel three-dimensional (3D) NAND flash memory

• Autores: Bo Wang, Bin Gao, Huaqiang Wu, He Qian
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 78, 2017, págs. 80-84
• Idioma: inglés
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• Resumen

  • Abstract This paper presents a novel vertical-channel three-dimensional (3-D) NAND flash structure with robust reliability. By employing a more reliable selector, the proposed structure overcomes the key drawback of the conventional 3-D NAND flash which is caused by charge storage in global select gate (GSG) and string select gate (SSG). Based on TCAD simulation, the conventional structure shows a threshold voltage shift of more than 1.5V, while the proposed structure is immune to this issue completely. Key parameters were analyzed to offer guidance on design and fabrication. Thickness of gate dielectric and thickness of SiO2 spacing layer beneath GSG are key parameters for the electrical property of select gate, and thus should be designed accurately.