Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

• Autores: Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 57, 2016, págs. 53-58
• Idioma: inglés
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• Resumen

  • AbstracMeasurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.