Radio-Frequency Silicon LSI's for Personal Communications
M. Ishikawa, T. Tsukahara
págs. 515-524
Analog LSI Circuit Design Issues for Optical Transmission Systems
Y. Akazawa
págs. 525-536
Wide Dynamic Range MOS Analog Inverter
K. Takakubo
págs. 537-543
Compact Realization of Phase-Locked Loop Using Digital Control
M. Izumikawa, M. Yamashina
págs. 544-549
Hierarchical Word-Line Architecture for Large Capacity DRAMs
T. Morotani, T. Sugibayashi, M. Takada
págs. 550-556
A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM
H. Yahata
págs. 557-565
A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology
K. Kozaru
págs. 566-572
Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
S. Shiratake
págs. 573-581
A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs
K. Furutani
págs. 582-589
A 6.93-µm2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
M. Minami
págs. 590-596
Low Consumption Power Application of Pulse-Doped GaAs MESFET's
N. Shiga
págs. 597-603
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