Flexible GF(2^m) arithmetic architectures for subword parallel processing ASIPs
W. M. Lim, M. Benaissa
págs. 291-301
M. S. Abadir, J. Bhadra
págs. 302-312
Improving energy-efficiency in high-performance processors by bypassing trivial instructions
A. Baniasadi, E. Atoofian
págs. 313-322
Applying the Handel-C design flow in designing an HMAC-hash unit on FPGAs
M. W. El-Kharashi, E. Khan
págs. 323-334
págs. 335-347
Employing pipelined thinning architecture for real-time fingerprint verifier
X. Z. Chen, P. Y. Hsiao
págs. 348-354
Trace cache miss tolerance for deeply pipelined superscalar processors
G. Pitigoi-Aron, G. Reinman
págs. 355-361
System integration by request-driven GALS design
E. Grass, M. Krstic, C. Stahl
págs. 362-372
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