Electrical characterization of reliability in advanced silicon-on-insulator structures for sub-22nm technologies
- Autores: Carlos Marquez Gonzalez
- Directores de la Tesis: Francisco Gámiz Pérez (dir. tes.), Noel Rodríguez Santiago (dir. tes.)
- Lectura: En la Universidad de Granada ( España ) en 2017
- Idioma: inglés
- Tribunal Calificador de la Tesis: Andrés Godoy Medina (presid.), Luca Donetti (secret.), Akiko Ohata (voc.), Philippe Galy (voc.), Paul Hurley (voc.)
- Programa de doctorado: Programa de Doctorado en Física y Ciencias del Espacio por la Universidad de Granada
- Materias:
- Enlaces
- Tesis en acceso abierto en: DIGIBUG
- Resumen
The aim of the work herein presented in this PhD thesis is to study, through the electrical characterization, the reliability issues derived from the scaling down of the state-of-the-art Silicon-On-Insulator transistors. The miniaturization of the dimensions of the transistor has been the trend which semiconductor industry has followed in order to increase the number of devices per chip and, subsequently, the performance of the circuit. However, the reduction of the gate oxide thickness and the gate length, mandatory to follow the scaling rules, have implied the introduction of new dielectric materials and device structures. These advances have also introduced new instability sources which may affect the performance and the reliability of the devices.
The first reliability issue studied in this PhD thesis is the bias instability, which affects the electrical characteristics of a MOS transistor when the gate is stressed with relatively high voltage. In this context, the instabilities of bare SOI wafers are characterized by using a point-contact method know as Pseudo-MOS technique.
This characterization technique permits to study both negative and positive bias stress in electron and hole channels. The comparison of SOI wafers with different film thicknesses and surface quality, together with fully processed MOSFETs, have pointed out the origin of the instability to be the interface between the native (spontaneous) oxide and the channel. The results allow the semiconductor manufacturer to pay more attention to the areas most vulnerable to sources of instability. Another instability source, directly derived from the introduction of new dielectric materials as gate oxide and the reduction of the signal levels, is known as Random Telegraph Noise. This effect is explained by the stochastic trapping/ detrapping behavior of the carriers of the channel into the switching oxide traps in dielectrics. In this work, a new protocol to study the Random Telegraph Noise in state-of-the-art Silicon-On-Insulator transistor is introduced. The protocol combines both a current-time scanning characterization and a low-frequency noise spectral density characterization, to identify the single-trap Random Telegraph Noise devices in optimum bias conditions. This experimental method has allowed to monitory the distribution of traps over the transistors on wafer, to determine the physical characteristics of the trap, to study the effect of the temperature on the characteristic times and, to characterize the impact of the substrate bias on the Random Telegraph Noise fluctuation. The reduction of the gate length of the transistor has allowed to introduce more devices in the same area, however, if the supply-voltages are not reduced, to hold the voltage compatibility with older circuit technologies, the electric fields in the transistor increase. The increment in the lateral electric field implies the appearance of some reliability issues, usually known as short channel effects. Impact ionization is one of these effects, where the highly energetic electrons, which move from the source to the drain, knock electrons out of their bound state and promote them to a state in the conduction band, creating electron-hole pairs.
In this PhD thesis impact ionization has been characterized in state-of-the-art Silicon-On-Insulator transistors. The study has been carried out in specifically fabricated five-terminal transistors with body-contact. This structure overcomes the fact that Silicon-On-Insulator structures do not permit a direct contact with the channel of the transistor due to the buried oxide. In this context, thin and ultra-thin body-contacted transistors have been characterized revealing the large influence of the channel length of the device on the body potential. A severe loss of electrostatic control of the body by the gate due to hole injection has been pointed out. Additionally, the dependence of the impact ionization with the substrate bias has been studied.
Finally, electrical characterization of laser-assisted reduced graphene oxide is carried out by using point-contact techniques. The experiments shed light on the role of the point-contact when extracting the intrinsic resistivity of the material. The study reveals that the final optimized reduced graphene oxide samples present a promising conductivity, comparable to that of large graphene sheets obtained by chemical vapor deposition methods.
