A methodology and framework to assist in the architecture design and functional verification of complex electronic systems

• Autores: Koldo Tomasena
• Directores de la Tesis: Igone Velez Isasmendi (dir. tes.), Juan Sevillano Berasategui (dir. tes.)
• Lectura: En la Universidad de Navarra ( España ) en 2013
• Idioma: inglés
• Número de páginas: 435
• Tribunal Calificador de la Tesis: Andrés García-Alonso Montoya (presid.), Andoni Irizar Picón (secret.), Miguel Soto Rodríguez (voc.), Francisco Javier del Pino Suárez (voc.), Jon Legarda Macon (voc.)
• Materias:
  • Ciencias tecnológicas
    • Tecnología electrónica
      • Diseño de circuitos
• Enlaces
  • Tesis en acceso abierto en: Dadun
• Resumen

  • An integrated, powerful and flexible development environment has been created in this research work in order to simulate and verify electronic systems starting from a very high abstraction level. The system architecture design, the algorithm tuning and the functional verification can be performed efficiently early in the development process by means the proposed contributions