Resumen de Integració de transistors verticals d'un sol electró en tecnologia cmos
This thesis presents the investigations performed towards the integration of Single Electron Transistor (SET) into Complementary Metal-Oxide-Semiconductor (CMOS) technologies.
Two of the main drives in semiconductor industry are device miniaturization and power consumption reduction. In the most advanced nodes, three-dimensional architectures have gained significant importance to increase the integration density, being vertically arranged devices the most suitable candidates for the ultimate generations. On the other hand, single electron devices are examples of ultra-low power consumption circuits.
In this work, the fabrication of a SET based on a vertical nanowire and its co-integration with CMOS technology is addressed. The starting point is a Si/SiO2/Si nanopillar with Si nanodots in the intermediate SiO2 layer, acting as quantum dot of the system. The subsequent gate and drain electrodes are placed all-around the embedded oxide and on contact with the pillar cap, respectively. Pillar integrity and its electrodes contacting are validated by structural characterization.
While SET integration in large-scale production is still challenging, its combination with CMOS technology benefits from the technological maturity of integrated circuits processing, overtaking SET intrinsic drawbacks as background noise or device instability. This work also reports the CMOS compatible and monolithic fabrication of a conventional planar transistor co-integrated with a vertical SET. The process fabrication is adapted to fulfil the restrictions imposed by the pre-fabricated SET, such as reduced thermal budget, protective layers and modified doping.
The monolithic fabrication of vertical SET and planar transistors is demonstrated; the pillar integrity is preserved, and the fabricated transistors operate at optimum conditions for SET compatibility.
