Compact dc modelling of short-channel effects in organic thin-film transistors
- Autores: Prüfer Jakob Markus
- Directores de la Tesis: Benjamín Iñiguez Nicolau (dir. tes.), Alexander Gunther Klös (dir. tes.)
- Lectura: En la Universitat Rovira i Virgili ( España ) en 2022
- Idioma: inglés
- Tribunal Calificador de la Tesis: Joaquim Puigdollers González (presid.), Antonio Ramon Lázaro Guillén (secret.), Yvan Bonnassieux (voc.)
- Programa de doctorado: Programa de Doctorado en Tecnologías para Nanosistemas, Bioingeniería y Energía por la Universidad Rovira i Virgili
- Materias:
- Enlaces
- Tesis en acceso abierto en: TDX
- Resumen
In the last decades, organic thin-film transistors (TFTs) have been subject of intense research and have become promising candidates for the possible use in novel electronic applications. The solubility of organic materials enables to fabricate organic electronics by inkjet printing or roll-to-roll processing at relatively low temperatures, which reduces additionally the manufacturing costs. Furthermore, several substrate materials can be applied such as glass, plastic foils or paper [1]. This makes the OTFTs potentially useful for sensor and active-matrix arrays [2] [3]. In order to improve the static [10], [11] and the dynamic [12-14] performance of the TFTs, a more aggressive downscaling of the channel length is performed [15]. Thereby, various short-channel effects, such as a degradation of the subthreshold swing, a dependence of the threshold voltage on the channel length (threshold voltage roll-off) and the drain-source voltage (drain-induced barrier lowering effect) gain influence on the current-voltage characteristics of the organic TFTs. These effects are known from crystalline metal-oxide-semiconductor field-effect transistors (MOSFETs) and arise from the electrostatic influence of the source and the drain contacts on the surface-potential barrier along the channel in the semiconductor layer. Furthermore, the charge-carrier injection and ejection at the Schottky barriers at the metal/semiconductor interfaces of the source and the drain contacts, respectively, cause a non-linearity of the output curves in the linear regime of operation. The design of integrated circuits requires time-efficient and accurate simulations. Therefore, circuit simulators apply compact models, which must capture the relevant device physics and reproduce the electrical TFT characteristics [4] [5]. These are determined by the general device structure (coplanar or staggered), the properties of the applied materials (e.g., orbital energies, charge-carrier mobility, charge-trap density, etc.), the geometrical dimensions (e.g., thicknesses of the contacts, channel length, semiconductor thickness, gate-dielectric thickness, etc.), the bias conditions (potential at the gate, the source and the drain electrodes), and the temperature. Consequently, the development of improved physics-based compact models to support meaningful circuit designs increased in the last decades [6-9].
In this dissertation, the short-channel effects (threshold voltage roll-off, subthreshold swing degradation and DIBL) and the influence of the Schottky barriers at the source and the drain contacts on the current-voltage characteristics are modelled for the coplanar and the staggered TFT architecture by deriving compact analytical physics-based equations. Finally, methods are presented to implement each model equation into any arbitrary compact current model.
The coplanar and the staggered short-channel models are based on two-dimensional solutions of the Laplacian differential equation. Thereby, the potential problems of both geometries are firstly simplified and subsequently, their boundary conditions are decomposed into two separated problems: the even and the odd mode. Both modes superposed lead to the original potential problems. The boundary conditions for the gate, the drain and the source electrodes depend on the conditions of the original potential problems. These are chosen to obtain defined conditions along the axis of symmetry in both geometries, which is located in the centre of the channel perpendicular to the gate electrode. As a result, the potential problems of both modes are reduced to only one half of the geometry, the solutions of which are sufficient to calculate the potential of the entire TFT. Finally, Laplace’s equation of the source-side half of both modes is solved by applying the Schwarz-Christoffel transformation. From these solutions, the surface-potential barrier can be extracted along the most leaky path of the drain-source current. The change of the maximum barrier height caused by the channel length, the gate voltage and the drain voltage serve as a basis to define the model equations of the short-channel effects.
In case of the most leaky path of the drain-source current, simulated coplanar and staggered TFTs with a channel length of 100 nm in TCAD software have shown that the location of the most leaky path differs with regard to the gate-source voltage. If an organic TFT is operated in the on state, the hole density is highest at the gate-dielectric/semiconductor interface, whereas in the subthreshold regime, the largest hole density can be observed at the ambient/semiconductor interface. Since the subthreshold swing and the DIBL models are extracted in the subthreshold regime, the maximum barrier height must be extracted at the ambient/semiconductor interface. In case of the threshold voltage roll-off, TCAD simulations have shown that despite this physical interpretations the best agreement is obtained by a maximum barrier height extraction at the gate-dielectric/semiconductor interface. Finally, the short-channel model equations are implemented into a charge-based dc model valid for long-channel organic transistors. Thereby, the change of the maximum barrier height along the ambient/semiconductor interface with respect to the change of the gate voltage is determined and multiplied by the subthreshold swing parameter of the charge-based dc model. Similarly, the threshold voltage of the long-channel compact dc model is reduced by the model equations of the threshold-voltage roll-off and DIBL, which both calculate a shift of the threshold voltage. Any arbitrary compact dc model that is defined by the threshold voltage and the subthreshold swing can implement the short-channel model equations in the same way.
Concerning the source contact, the formed Schottky barrier at the metal/semiconductor inter-face is modelled as reverse-operated diode in series with the intrinsic organic TFT. Thus, in all regimes of operation, the charge carriers must overcome the barrier to contribute to the drain-source current. However, the barrier height is sensitive to the electric field due to im-age charges (Schottky barrier lowering effect). To calculate the actual barrier height in all regimes of operation, expressions for the electric field for the coplanar and staggered TFTs are derived. Therefore, in case of the coplanar structure, the Schwarz-Christoffel transformation is applied to solve Poisson’s equation of the two-dimensional potential problem. By contrast, the electric field at the source/semiconductor interface in the staggered TFT is reduced to a one-dimensional problem, which is modelled as parallel-plate capacitor. Finally, the current injection is calculated by the thermionic-emission current equation, which is subsequently applied to define an equivalent field-dependent resistance that captures the influence of the Schottky barrier as a parasitic element.
The influence of the Schottky barrier at the drain contact on the current-voltage characteristics is modelled by a generic compact modelling scheme, which defines the voltage drop across the barrier on the basis of the current of a barrier-less transistor in the deep saturation regime. Here, the current-limiting impact of the drain barrier on the drain-source current can be neglected even for quite larger barrier heights. Thus, the voltage drop across the drain barrier can be determined by the thermionic-emission current equation and the drain-source current of a barrier-less TFT. If no drain-source voltage is applied, the voltage drop across the drain barrier is obviously zero. The regime between Vds = 0 V and the drain- source voltage at which the voltage drop across the drain barrier saturates is modelled as linear mathematical function with regard to the drain-source voltage. In order to avoid numerical problems, a smoothing function is applied that leads to a single compact equation. To implement the impact of the drain barrier, the drain-source voltage of the organic TFT is reduced by the voltage drop across the drain barrier.
For the verification of the short-channel models, TCAD simulations of staggered and coplanar TFTs with channel lengths ranging from 0.1 to 10 µm are conducted to obtain the transfer characteristics of each TFT. Additionally, the electrostatic potential along several cutlines parallel to the gate-dielectric/semiconductor interface distributed over the entire semiconductor thickness is computed. Subsequently, the short-channel effects are extracted from these TCAD simulations and compared to the models. The comparisons show that the analysis of the most leaky path with regard to the gate voltage is valid and further, the compact short-channel models are in good agreement with the extraction from the transfer characteristics as well as the electrostatic potentials.
Furthermore, the charge-based dc model, which is valid for long-channel organic transistors, is extended by the short-channel model equations and the models of the Schottky barriers at the contacts. The extended compact dc model is verified by measured current-voltage characteristics of fabricated staggered and coplanar TFTs, which show the influence of each short-channel model and the impact of the Schottky barriers on the current behaviour in the linear regime of the output characteristics. The extended compact current model is capable to reproduce the current-voltage characteristics of the fabricated coplanar and staggered TFTs with good accuracy.
Finally, the excellent scalability with respect to the channel length of each model could be demonstrated, since the model parameters during the verification of transistors with different channel lengths were equal. In general, the models are not limited to organic TFTs, but, they can also be applied in inorganic TFTs.
