Charge-based compact modeling of capacitances and low-frequency noise in organic thin-film transistors
- Autores: Jakob Simon Leise
- Directores de la Tesis: Alexander Gunther Klös (dir. tes.), Benjamín Iñiguez Nicolau (dir. tes.)
- Lectura: En la Universitat Rovira i Virgili ( España ) en 2022
- Idioma: inglés
- Tribunal Calificador de la Tesis: Ángel Luis Álvarez Castillo (presid.), François Lime (secret.), Radu Sporea (voc.)
- Programa de doctorado: Programa de Doctorado en Tecnologías para Nanosistemas, Bioingeniería y Energía por la Universidad Rovira i Virgili
- Materias:
- Enlaces
- Tesis en acceso abierto en: TDX
- Resumen
In the past decades, the research field of organic electronics has gained significant interest. Thin-film transistors (TFTs) can be fabricated using organic semiconductors for the active device region [1]. Organic semiconductors allow for a comparatively easy processing of transistors including the possibility to fabricate transistors at room temperature on flexible substrates like plastic foils or paper [2-5] which makes them interesting for the fabrication of novel electronics like flexible displays. Additionally, organic semiconductors can be solution-processed which allows for a fabrication of organic devices using inkjet printing techniques and spin coating [6].
A general property of every transistor is that charge carriers are present in the conductive region (the channel) of the transistor. The number of charge carriers is dependent on the applied terminal voltages. Since the charges cannot be created or disappear by recombination in the transistor, they have to enter or leave the device through the terminals (drain, gate and source) [7]. As a consequence, capacitive charging currents are present when the transistor is operated in a non-steady-state operation point, i.e. under conditions, where the terminal voltages vary with time. In nearly every analog or digital circuit, the signals applied to the terminals of the transistors are time-dependent. Thus, for the prediction of the behavior of an electrical circuit, the capacitive behavior of a transistor is of major importance. In this thesis, a charge-based compact model for the description of the total charges associated with the gate, the drain, and the source terminals of the transistor is developed. This model captures the intrinsic charges in the channel region and as well charges stored in extrinsic regions such as gate-to-contact overlap regions and fringe regions. The charges in the gate-to-contact overlap regions are modeled in dependence on the transistor architecture (staggered and coplanar). In coplanar transistors, the gate-to-contact overlap regions are treated as parallel-plate capacitors. By contrast, in staggered transistors, the overlap regions need to be treated as a series connection of the gate dielectric and the depleted organic semiconductor. If the semiconductor is driven into accumulation, the voltage drop across the series connection saturates and accumulation charges are taken into account.
A charge based DC model [8] serves as the basis for the calculations presented in this work. Assuming a drift-diffusion transport, a closed-form description of the three terminal charges under quasistatic conditions is derived. The term "quasistatic" refers to an operation point where the charges can instantly follow the applied signals so that at every time point, the charges are the same as they would be under steady-state operation conditions [7]. However, if the time derivatives of the applied terminal voltages are very large, the time-dependent propagation of the charges in the device is of importance. Thus, in this work, two different approaches are used in order to capture this non-quasistatic behavior. For long-channel transistors comprising small contact resistances, a macro model is used which treats the transistor as a series connection of several small transistors. If, by contrast, the transistors have short channel lengths and are operated at high frequencies, this channel-segmentation approach is not sufficient. For this purpose, empirical scaling functions are introduced which alter the areas in the transistor that are taken into account for the total charge calculation.
Three-dimensional effects are taken into account based on finite-element simulations. Organic thin-film transistors often have fringe-regions, i.e. areas where the gate stack is in contact with the organic semiconductor but which are beyond the geometric channel center defined by the patterned source/drain contacts. In such regions, an effect denoted as current spreading occurs. Furthermore, charges are accumulated everywhere where the gate stack is in connection to the organic semiconductor. The charge-based DC model is modified in order to account for the current spreading. The three-dimensional accumulation of charges is included in the charge model.
In general, the source/drain electrodes of an organic transistor consist of a metal which results in metal-to-semiconductor junctions. If the work function of the metal is not aligned with the highest occupied molecular orbital energy of the organic semiconductor, there arise Schottky barriers resulting in contact resistances [9,10]. These play an essential role especially in short-channel transistors where the channel resistance becomes small in comparison to the contact resistances. As an addition, in this thesis, a semi-empirical approach to account for the influence of the contact resistances on the total charges is presented.
In addition to the capacitive behavior, another time-dependent effect plays a role in transistors: the noise which is a small fluctuation of the current around its steady-state value. There are different mechanisms leading to noise such as mobility fluctuations or charge-carrier-number fluctuations [11]. In this work, a compact modeling scheme is presented allowing for both of the aforementioned noise types to be captured.
The models which are developed in this work are verified with regard to measurements of transistors and circuits and to results of a finite-element simulation using the simulator Sentaurus TCAD. The basic charge model is verified by capacitance measurements of a staggered long-channel organic TFT and by TCAD simulations of staggered and coplanar organic TFTs. Furthermore, the model is implemented in the hardware description language Verilog-A in order to demonstrate the good circuit functionality of the model when compared to measurements of a differential amplifier. The channel-segmentation model is verified by frequency-dependent admittance measurements of a staggered long-channel transistor and by a TCAD simulation. The short-channel capacitance model at high frequencies is verified by means of scattering-parameter measurements of staggered and coplanar transistors comprising asymmetrical gate-to-source and gate-to-drain overlap lengths. The noise model is compared to measurements of polymer-based organic TFTs and to TCAD simulations. An overall good agreement of the different model components is observed.
The models presented in this thesis are of scientific significance since the overall behavior of a transistor that is employed in a circuit simulator is properly described only if time-dependent effects are taken into account. By means of theoretical thoughts and finite-elements simulations, equations covering these effects in organic thin-film transistors are developed. The model exhibits a good agreement with respect to measurement results and finite-element simulations.
