Resumen de Study of variability phenomena on CMOS technologies for its mitigation and exploitation
Variability phenomena in CMOS technologies have become a growing concern in recent years. One of the main reasons for this is the continued scaling of the transistor dimensions. This scaling has considerably increased the impact that these phenomena can have on different transistor parameters. Variability phenomena can be divided in two categories: Time‐Zero Variability, which occurs during the manufacturing process, and Time‐Dependent Variability, which occurs along time due to the operation of the circuits. Some Time‐Dependent Variability phenomena are caused by the trapping and detrapping of charge carriers in defects present in the transistors. In older technologies, a very high number of defects was present in each device, so that the total impact of these defects would average out and the impact of Time‐Dependent Variability would be observed as deterministic. As the size of these transistors shrinks, the number of these defects decreases. Therefore, in newer, deeply‐scaled technologies, each transistor contains a small number of defects, and Time‐Dependent Variability phenomena are observed as stochastic. This represents an important qualitative change, since different transistors (and therefore circuits) operating under the same exact conditions for the exact same time will degrade differently. This fact should be reflected in Time‐Dependent Variability models and simulation tools. In the first part of this Thesis, the characterization of different Time‐Dependent Variability phenomena is tackled, and a strategy to accurately model those phenomena using the data extracted during the characterization tests is developed. This strategy allows to model the phenomena accounting for their stochastic nature. In particular, the studied Time‐Dependent Variability phenomena that are studied are Random Telegraph Noise and Bias Temperature Instability, and the model constructed is the Probabilistic Defect Occupancy model, which aims at describing the trapping and detrapping of charge carriers by defects along time depending on the operation conditions. Apart from that, different techniques to analyze the characterization data are presented and discussed, highlighting the advantages of each one. In the second part of this Thesis, the focus is shift to the exploitation of Time‐Zero Variability. This is done through the concept of Physically Unclonable Functions, which make use of random, unpredictable variations in the manufacturing process. These variations can lead to “circuit fingerprints” that can be useful in different cryptographic applications. In this Thesis, the focus has been set on SRAM‐based Physically Unclonable Functions. In particular, the goal has been to develop a method that improves the reliability of such a Physically Unconable Function under different conditions, such as when circuit degradation is considered, or under voltage or temperature variations. This method has been experimentally tested using a chip containing an SRAM cell array designed for this purpose. To summarize, this Thesis has approached variability phenomena in two very different ways: to mitigate their potentially harmful impact on circuits, and to exploit them for cryptographic applications. In both cases, experimental tests have been performed to support the corresponding theoretical developments.
