Resumen de Mems microphone digital interfaces based on open-loop vco-adcs
In recent years, the use of voice communication and speech recognition applications has increased. This has resulted in an evolution of the voice processing algorithms and a progress of miniaturized high-performance microphone sensors. The presence of these small microphones in the market is increasingly strong due to its use in mobile devices, wearables, active noise cancellation, in video recording applications or to conform beamforming arrays, where more than two microphones are included in the same device to detect sound in a particular direction while blocking the undesired sound originated from other directions.
A microphone is a transducer that converts the acoustic waves into electrical signals, which can be amplified as an analog signal or post-processed with an analog-to-digital converter (ADC). According to the sensing mechanism, the microphones can be mainly classified into moving coil, piezoelectric, piezoresistive, optical and capacitive sensors. In the moving coil topology, also known as dynamic microphones, a coil attached to a diaphragm within a magnetic field is displaced, inducing an electric current proportional to the sound waves variation. In the piezoelectric type, the acoustic pressure generates electric charges at the microphone plates, while in the piezoresistive devices, the sound pressure variation induces changes in the electrical resistance of the piezoresistive material in the microphone membrane. In optical microphones the sound is converted to an electrical signal by sensing the intensity of a light incident on a reflective diaphragm. In the case of capacitive microphones, the acoustic stimuli change the capacitance between diaphragm and backplate, which can also be translated into an electrical signal.
One of the most interesting microphone topologies is based on the capacitive acoustical sensors, which are usually implemented with microelectromechanical systems (MEMS), presenting a low noise level, a flat frequency response and a high sensitivity. To have a fully functional MEMS microphone, the MEMS acoustical sensor must be connected to an application-specific integrated circuit (ASIC), in which a complementary metal oxide semiconductor (CMOS) readout circuit is implemented. This way, the MEMS sensor acts as a transducer to convert the sound pressure level into an analog signal, proportional to the measurand changes. Then, with the readout circuit, the analog signal generated in the sensor can be conditioned and converted to a digital bitstream, in order to be post-processed with a system-on-chip (SoC) or a microcontroller.
In general, current trends in the development of audio acquisition interfaces lead to a reduction in area and power consumption, without sacrificing the high acoustic performance. These requirements are mainly imposed by the nature of use of the devices in which the MEMS microphones are integrated, that is, portable devices with a critical battery running time and a small form factor.
The shrinking of modern deep submicron technologies in CMOS very large-scale integration (VLSI) circuits leads to an efficiency improvement in the digital circuitry. The main benefits are the reduced power consumption, the higher operating speeds and the smaller die area. In 1965 Gordon E. Moore predicted that the number of transistors in a dense integrated circuit (IC) will continue to growth exponentially. This is known as Moore’s law, and it states that the number of transistors in a single silicon chip doubles about every two years. Moore’s law still applies in 2020 with advanced CMOS manufacturing techniques reaching the current 5 nm CMOS fabrication process. However, this technology downscaling imposes a voltage supply reduction, limiting the voltage headroom of transistors. Moreover, the noise, the mismatch and the gain of the transistors are affected. These issues make it increasingly difficult to design analog circuitry. Because of this, in recent years there has been a trend to implement ADC designs with a mostly digital architecture, replacing the functionality of analog circuits with digital circuitry.
Time-encoding technique is a good candidate to overcome the limitations of the classical voltage-encoding systems, like the traditional sigma-delta (ΣΔ) modulators. In time encoding based ADCs the information contained in the analog input signal is encoded into the frequency, or another time property, of a two-level signal, which can be post-processed with pure digital sub-systems. By doing this, the area and power consumption of the ADC can be improved, taking advantage of the CMOS technology downscaling.
A time-encoding ADC for MEMS microphones can be implemented with a voltage-controlled oscillator (VCO), whose frequency will be modulated according to the changes in the MEMS acoustical sensor. Then, the oscillation frequency variation can be tracked with a digital circuit to generate the converter output bitstream. Last years, VCO-based ADCs have gained a great attention due to their mostly digital implementation, among other benefits. Furthermore, digital circuitry can be implemented in a semi custom design flow with available computer-aided design (CAD) tools, simplifying and making less costly the design process. This dissertation proposes the development and implementation of digital interfaces for capacitive MEMS microphones based on open-loop VCO-ADCs.
The design of open-loop VCO-ADC interfaces for sensors can be divided into two different approaches. The first one is associated with the implementation of the input signal-to-frequency conversion stage, which consists of the oscillator and the circuit for the interconnection between sensor and oscillator. This part of the converter translates the analog input signal variation, which is a voltage signal in a capacitive MEMS microphone, into a frequency variation of the oscillator output signal. The design of this stage is mainly aimed to reduce the flicker and thermal noise contributions. In the oscillator, these noise sources appear as phase noise, which is demodulated after sampling as a low frequency noise. The phase noise can be mistaken for the frequency variation induced by the ADC input signal. Consequently, this phenomenon will have a negative impact on the ADC accuracy. In this thesis, an equivalent technique to chopping in conventional switched capacitor circuits is proposed to mitigate the flicker noise in a capacitance-controlled ring oscillator (RO) readout circuit. The flicker noise impact is reduced by modulating it to frequencies above the bandwidth of interest and then filtering. The proposed flicker mitigation technique has been validated by transistor level simulations in 130 nm CMOS technology. However, the performance of the proposed technique can be limited in a real implementation by the parasitics of the capacitive MEMS sensor.
Another limiting factor inherent to the oscillator block in open-loop architectures is the non-linear relationship between input signal and output frequency. Depending on feedback usage, oscillator-based ADCs can be classified in open-loop or closed-loop architectures. In closed-loop configuration, the oscillator is embedded into a feedback loop together with a digital-to-analog converter (DAC). The existence of a DAC in the loop does not imply extra resolution if compared with the open-loop architecture, but the effect of the oscillator non-linearity in the ADC output is mitigated. However, some of these implementations require complex data-weighted averaging (DWA) or DAC linearity calibration techniques. In contrast, the open-loop topology does not use feedback, and consequently there is no DAC to be calibrated. This means that the complete range of the oscillator tuning curve is employed and therefore, the oscillator non linearity would affect the ADC performance. Nevertheless, the linearity obtained with open-loop oscillator-based ADCs may be tolerable for low cost digital microphones without applying linearity enhancement techniques. Thus, the time-encoding ADC implementations proposed in this dissertation are based on open-loop architectures, avoiding the need for complex calibration mechanisms.
Usually, the estimation of the degradation caused by these impairments is done by transient simulations that consume a significant computational time. This complicates the iterative optimization in terms of phase noise, distortion, power consumption and area during the oscillator design process. In this thesis is proposed an input-referred phase noise (IRPN) model that makes use of periodic steady state (PSS) and periodic noise (PNOISE) simulations to enable an oscillator iterative optimization with reduced computational times.
The second approach in the design of open-loop VCO-based ADCs for sensors is related to the frequency-to-digital conversion stage. This fully digital circuit converts the frequency-encoded output of the oscillator into a digital bitstream that reflects the ADC input signal variation. Among the most important design goals of this block are the converter resolution improvement and the power-efficient implementation. This is addressed in this thesis with the proposal of two different architectures for the VCO based ADC quantization circuit. The first architecture utilizes a time-to-digital converter (TDC) to improve the converter resolution without increasing the noise shaping order or the system sampling clock, while the second one is based on a novel power-efficient coarse fine quantization method.
The idea behind the basic TDC architecture applied to the quantization circuit of a VCO-based ADC has been described in this dissertation. This solution is based on the use of a digital delay line, which emulates a much higher sampling frequency compared to the original ADC sampling clock, when connected to one of the VCO output phases. The resolution enhancement obtained by using the TDC delay line architecture can also be justified considering the equivalence between the VCO operation and the pulse frequency modulation (PFM) theory. The resolution improvement obtained with the delay line has been proven in this dissertation by behavioural simulations. Also, the possible impact of non-idealities on the TDC system, such as delay mismatch and jitter in the clock has been analysed. Behavioural simulations show a faster system degradation for longer delay lines in presence of mismatch in the delay line units. For the clock jitter influence analysis, simulations show a better tolerance to this impairment than in continuous time sigma-delta (CT-ΣΔ) modulators. Two equivalent solutions in terms of resolution have been presented for the delay line post processing circuit but generating different bit formats at the ADC output. A single-bit or a multi-bit output bitstream can be generated with this VCO quantization architecture, depending on the audio application requirements.
To prove the feasibility of the presented VCO-based ADC architecture employing a TDC to increase the converter resolution, a CMOS protype has been designed and implemented to interface a capacitive MEMS microphone. As a requirement of the target audio application, the ADC output has been accommodated in a multi-bit bitstream, which can be easily transformed into any standard audio interface by means of digital signal post-processing, without requiring a DWA technique or feedback DAC linearity calibration, compared to a multi-bit switched-capacitor sigma-delta (SC-ΣΔ) modulator. However, if a single-bit signal is preferred, the multi-bit output can be processed with a noise-shaper coder. The proposed data converter is composed of two identical single ended channels which, combined in a pseudo-differential configuration, present full integration with dual backplate (DBP) MEMS microphones. The output of the capacitive MEMS sensor is coupled into the ADC input via an impedance converter, generating the voltage signal that sets the frequency of a 5-phase RO. The oscillator output, after a level shifter, is divided by a factor of four in order to adjust the oscillation frequency and to make it compatible with the implemented demodulation circuit. The frequency-modulated signal obtained at the output of the divider is passed through a 31-stage delay line. The output signals of the delay line are sampled and demodulated applying the first-order difference. By using a thermometer to binary (T2B) converter, the demodulated signals form the multi-bit sequences at the output of the single-ended channels. The differential digital output of the converter is given by the two’s complement subtraction of both single-ended branches.
The proposed readout circuit has been prototyped in a 130 nm CMOS process, occupying an active area of 0.12 mm2. It has been bonded to a standard MEMS microphone sensor for the acoustical characterisation. Some electrical measurements have also been done by using an array of silicon capacitors connected to the ADC input, replicating the MEMS microphone nominal capacitance. Prototype electrical measurements show a peak signal-to-noise ratio (SNR) of 90.82 dB-A and a peak signal-to-noise and distortion ratio (SNDR) of 77.89 dB-A, over the 20 kHz audio bandwidth with a system sampling frequency (fs) of 20 MHz. The achieved dynamic range (DR) is 100 dB-A while the acoustic overload point (AOP) is reached at 130 dBSPL. The measured current consumption is 750 μA with the ASIC powered at 1.8 V. Audio measurement results were limited by the MEMS acoustic packaging, among other factors.
The second architecture proposed in this dissertation for the frequency-to-digital conversion stage of a VCO-based ADC, is based on a power-efficient data-scrambling coarse-fine quantization method, intended to mitigate synchronization and metastability errors. In this energy-efficient architecture, instead of using a multiple counter array connected to all the VCO output phases, a coarse counter is connected to one of the VCO output phases to accumulate the integer phase progression over a sampling period, while the state of the remaining phases is sampled with a register, tracking this way the oscillator fractional phase progression. A decoding and differentiator block combines the pivotal counter coarse estimation and the phase register fine correction into a multi-bit first-order noise-shaped sequence. The performance in terms of resolution achieved with the proposed system is similar to that of the multiple counter array scheme. Since the oscillation follows a known pattern, the information lost by removing the redundant counters can be inferred from the sampled oscillator phases.
A second ASIC including the presented coarse-fine architecture for a VCO-based ADC intended to be used in the readout circuit of a capacitive MEMS microphone, has been prototyped in a 130 nm CMOS process. In the proposed ADC, the MEMS sensor is read out using a high-voltage and high ohmic biasing circuit by placing an on-chip charge pump. Then, the acoustical signal applied to a DBP MEMS microphone is translated into a high impedance differential voltage signal at the ADC input nodes. By using a transconductance stage, a voltage-to-current conversion is implemented, generating this way the differential signals that drive two current-controlled oscillators (CCOs), each one built with an 11-phase RO. The number of rising edges per sampling period in all of the RO output phases is computed using two identical coarse fine counting circuits, one per channel. This quantization circuit implemented with the data-scrambling-based architecture is responsible for considerable power and area savings, as well as for the mitigation of synchronization and metastability errors. After applying a scrambling and descrambling process, coarse and fine first-order differences are combined together generating a 9-bit single-ended outputs. Then, the information of both channels is subtracted to generate a two’s-complement 10-bit first-order noise-shaped output signal. Finally, the data interface is completed with a 4th-order digital noise-shaper that transforms the 10-bit output bitstream into a 1-bit pulse-density modulated (PDM) sequence. Two operating modes have been implemented: a normal mode with fs = 2.4 MHz and 20 kHz of bandwidth, and a low power mode with fs = 768 kHz and 8 kHz of bandwidth. The noise shaper includes a programmable input gain stage to adjust the modulator full scale according to the different modes.
The implemented prototype occupies an active area of 0.04 mm2. Prototype measurements show a peak SNDR of 73.8 dB-A and 97 dB-A of DR in a 20 kHz bandwidth, while consuming 240 μW from the 1.5 V/1.2 V power supplies. In the reduced power mode, with relaxed oscillation parameters, it reaches 66.4 dB-A of SNDR peak, and 93 dB-A of DR in an 8 kHz bandwidth, with a power consumption of only 77 μW.
