Compact modeling of intrinsic capacitances in double-gate tunnel-fets
- Autores: Atieh Farokhnejad
- Directores de la Tesis: Benjamín Iñiguez Nicolau (dir. tes.), François Lime (codir. tes.), Alexander Gunther Klös (codir. tes.)
- Lectura: En la Universitat Rovira i Virgili ( España ) en 2020
- Idioma: español
- Tribunal Calificador de la Tesis: Benito González Pérez (presid.), Antonio Ramon Lázaro Guillén (secret.), Qing-tai Zhao (voc.)
- Programa de doctorado: Programa de Doctorado en Tecnologías para Nanosistemas, Bioingeniería y Energía por la Universidad Rovira i Virgili
- Materias:
- Enlaces
- Tesis en acceso abierto en: TDX
- Resumen
The rapid enhancement of the integrated circuits (ICs) in terms of the complexity, integration density, switching speed and efficiency, is due to the scalability of the metal—oxide—semiconductor field—effect transistors (MOSFET). In the last 50 years the size of these transistors has been constantly reduced following the Moor’s law. However, by reaching the channel length below 100 nm this trend has also reached its physical limits due to the short channel effects (SCEs). As a result of the SCE, further reducing the supply voltage and controlling gate leakage has become ever more difficult and challenging [1]. Therefore, from this point on, further scaling of MOSFETs was only possible through innovative structures and materials.
One of those structures which is considered as a viable successor of conventional MOSFETs is the tunnel—field—effect transistor (TFET). Studies have shown that TFETs are feasible to overcome the 60 mV/dec subthreshold swing of MOSFETs. It is due to the fact that the current transfer mechanism in TFETs is based on the band—to—band (B2B) tunneling instead of the thermionic emission in MOSFETs.
Hence TFETs can operate at a low supply voltage and therefore, have a lower power consumption. In comparison to MOSFETs they have a lower leakage current and are more stable against SCEs. Moreover, they are compatible with the complementary metal–oxide–semiconductor (CMOS) fabrication process [2-5].
However, there are still issues which challenge the production and implementation of TFETs. The main dilemma is enhancing the on—current of the TFET without worsening its subthreshold swing or increasing the off—current. A lot of studies have been carried out to find a way to tackle these challenges and represented methods which have proven to be successful.
In this early stage of TFET production, device simulations and compact models play an important role. Since they can give an insight about the behavior of the device and thus, save the time and high expenses on test wafers. For process and device simulations there are powerful programs such as Technology Computer–Aided Design (TCAD) existing. However, the simulations in this software are very time consuming and computationally demanding. Therefore, to enable circuit simulations including millions of transistors, compact models are required. These models need to be simple and fast but also accurate to provide circuit designers with useful and reliable results. A lot of investigations have been done on the DC modeling, calculating the potential characteristic and current in TFETs. But in order to do the transient analysis, the compact models for the capacitances and their charging behavior in TFETs are required as well. In fact, the switching speed of an IC is depending on the capacitances. Hence, the focus of this thesis lays on compact modeling of intrinsic capacitances in this type of transistors.
The compact charge—based capacitance model is derived for an n–type Si double—gate (DG) TFET. To calculate the total mobile charge of the channel a closed–form expression represented in [6] is implemented. In order to include the effect of the channel resistance, the compact DC model provided in [7] is used. Considering the structural parameters of the device which are under investigation and with the help of the DC model, first the drain current (Ids) is calculated. Then, the bias dependent channel resistivity by means of an empirical method is calculated. Having Ids and the channel resistance allows to calculate the voltage drop (ΔV) between the junction and the tunneling barrier in the channel. So, by applying the drain voltage (Vds) into the charge density closed–form expression, the mobile charge density at the drain junction is obtained and by implementing Vds − ΔV in the aforementioned formula, the mobile charge per gate area at the tunneling barrier in the channel close to the source junction is calculated. Then by taking the average of the two obtained values and multiplying the result with the area of the channel, the total mobile charge of the channel in the on–state is achieved.
The compact intrinsic capacitance model considers not only the on–state, but also the ambipolar–state of the transistor. Hence, in the ambipolar–state to calculate the charge density at the junction and tunneling barrier located close to the drain junction, respectively source voltage (Vs) and Vs −ΔV are used in the charge density expression.
The resulted capacitances were in a good agreement with the TCAD simulations. However, for further investigations the capacitance model was compared to the measured capacitances of a fabricated TFET. The first series of measurements corresponds to a p–type Si single—gate (SG) planar TFET which is fabricated in Juelich Forschungszentrum [8]. In the light of the measurement data, it has become clear that the parasitic elements are also needed to be integrated into the model. Hence, the parasitic effect of series resistances is incorporate into the capacitance model. To do so, it is considered that a resistance is connected in series at each terminal on the source and drain side.
Moreover, due to the fact that the DC model takes into account the effect of traps and the doping concentration in the source and drain regions, the capacitance model can also capture the influence of these parameters on the intrinsic capacitances of TFET. Nevertheless, the capacitive behavior of the fabricated TFET could still not be fully reproduced by model. It eventually has led to investigations into the influence of the Schottky barrier at the source and drain terminals on the intrinsic capacitances of the TFET and to the inclusion of this effect in the compact model. For this purpose, an empirical method is used. This method has evolved on the basis of the analysis of experimental data and shows that in the on–state at higher gate bias |Vgs| the capacitive behavior of the transistor is assigned not only to the gate—drain capacitance (Cgd ), but also partially to the gate—source capacitance (Cgs). In the ambipolar–state it illustrates that for higher |Vgs| the intrinsic capacitance of the TFET is not identical to the Cgs, but a sum of both capacitances Cgs and Cgd.
The results of the TCAD simulations of the planar structure including Schottky barriers at the terminals could not fulfill the expectation and reproduce a similar capacitive behavior as in measurements. Different approaches have been considered in order to find the correct values and ratios, with which at a certain gate bias one capacitance decreases and the other increases. In the end, with the help of TCAD Sentaurus, some Schottky diodes with different drain doping concentrations are simulated. By comparing their current with the measured Ids in a p–type TFET, the diode with a current closer to Ids is chosen and its conductance is extracted. This value is used to estimate the small signal conductance of the Schottky barrier in the TFET and to the inclusion of this effect in the compact model. For this purpose, an empirical method is used. This method has evolved on the basis of the analysis of experimental data and shows that in the on–state at higher gate bias |Vgs| the capacitive behavior of the transistor is assigned not only to the gate—drain capacitance (Cgd ), but also partially to the gate—source capacitance (Cgs). In the ambipolar–state it illustrates that for higher |Vgs| the intrinsic capacitance of the TFET is not identical to the Cgs, but a sum of both capacitances Cgs and Cgd.
The results of the TCAD simulations of the planar structure including Schottky barriers at the terminals could not fulfill the expectation and reproduce a similar capacitive behavior as in measurements. Different approaches have been considered in order to find the correct values and ratios, with which at a certain gate bias one capacitance decreases and the other increases. In the end, with the help of TCAD Sentaurus, some Schottky diodes with different drain doping concentrations are simulated. By comparing their current with the measured Ids in a p–type TFET, the diode with a current closer to Ids is chosen and its conductance is extracted. This value is used to estimate the small signal conductance of the Schottky barrier in the TFET and check the effect on the intrinsic capacitances. Finally, the model could show a similar pattern as in the measured data.
As the last step of verifying the model, it is compared to the measurement data of an n–type Si nanowire (NW) TFET. This structure is fabricated by imec, Belgium [9] and the measurements are provided by University of Sao Paulo, Brazil. Considering the cylindrical shape of the NW TFET, an equivalent DG channel length (lch) is used in the model. Furthermore, to cover the effect of the gate–source overlap in this structure, a constant parallel capacitance to the effective gate capacitance (Ceff) is implemented in the compact model. Then, with the help of the other already existing fitting parameters, the model is fitted to measurements. Comparing the results to the measured transfer characteristic and capacitances of the NW shows that the model is in a good agreement with the experimental dataAfter completion of the model, it is transferred to the Verilog–A language to enable circuit simulations. Using this compact TFET model, an inverter circuit is designed in Cadence Virtuoso. This circuit is then used to design a ring–oscillator. In order to examine the effect of the device parameters on the behavior of circuits, the simulations are performed using different parameters and properties for both p– and n–type TFETs. In each case, to ensure that both the DC and AC simulations of these transistors as a single element are reliable, firstly the results of the compact model simulations of the TFETs are verified against TCAD simulations. The circuit simulations based on verified transistors are then performed.
Bearing in mind the fact that with further innovation of the structures, the TFET on-current can be enhanced, the Ids [10], further circuit simulations are carried out to observe the behavior of TFET–based circuits in case they have a higher current. In this regard, output of the circuits based on the point tunneling TFET are compared to those based on line tunneling TFET. To do so, the compact model is firstly verified against TCAD simulations of a SG n–type TFET as well as p–type TFET. Then, the model is fitted for an ideal line tunneling case in which the on–current of the TFET is 1000 times higher than in the point tunneling case. Afterwards, simulations of an inverter and a 11–stage ring–oscillator are performed to compare the point and line tunneling setups. By means of these simulations the oscillation period of the ring–oscillator and from that the intrinsic inverter delay (τ) as a function of lch is obtained. The resulted τ for the point tunneling and line tunneling case are compared to each other and also to the corresponding data of a CMOS inverter. Finally, the average power consumption of the ring–oscillator by varying the supply voltage is achieved.
The intrinsic capacitance model is flexible and scalable and can be employed for various structures. In the course of the model verification it is shown, despite that the model is designed based on a short–channel Si DG n–type structure, its simplicity and flexibility allows simulations of various structures and also different types such as the p–type SG planar TFET and the n–type NW TFET. The model considers not only the on–state of the device but also the off– and ambipolar–state. It includes the non–ideal effects such as TAT or parasitic elements on the capacitances. The compact TFET model can provide a reliable insight about the intrinsic capacitances in TFET, is not time consuming or computationally demanding and is SPICE friendly.
There are still challenges that must be tackled before the TFETs can really meet all expectations and conquer the ICs. Researchers are constantly trying out new manufacturing methods, materials and structures to push the limits. With each step, new aspects of the TFET become apparent. In this case, fitting parameters can help to adapt the model and make it work without applying any complicated changes in the model.
