Experimental and simulation study of defects impact on the variability of mos structures
- Autores: Carlos Couso Fontanillo
- Directores de la Tesis: Marc Porti i Pujal (dir. tes.), Javier Martín Martínez (dir. tes.)
- Lectura: En la Universitat Autònoma de Barcelona ( España ) en 2018
- Idioma: español
- Tribunal Calificador de la Tesis: Raúl Rengel Estévez (presid.), David Jimenez Jimenez (secret.), Antonio Calomarde Palomino (voc.)
- Programa de doctorado: Programa de Doctorado en Ingeniería Electrónica y de Telecomunicación por la Universidad Autónoma de Barcelona
- Materias:
- Enlaces
- Tesis en acceso abierto en: TESEO
- Resumen
Over the last years, the information and its analysis have become the corner stone of the growth of our society allowing the sharing economy, globalization of products and know- ledge, block-chain technology, etc. Huge companies such as: Amazon, Facebook, Google... which were aware of the potential of these resources, are developing vast infrastructures in order to extract as much information as possible about our environment (Internet of Things) or ourselves (social media, smart-phones...), process this information (Big Data Centers) and transmit it quickly all over the world. However, this challenge requires electronic devices with higher performance and low power consumption, which cannot be developed using the conventional scaling techniques because the dimensions of devices have reached the atomic range. In this range of dimensions, the impact of the discreteness of matter and charge increases inevitably the variability of devices. Consequently, the scientific community is exploring new solutions such as, alternative device materials and/or structures, in order to overcome the different issues owing to the scaling. In this context, this thesis, which is structured in 7 chapters, will try to contribute to solve this problem, analyzing the impact of interface traps and defects on the device variability.
In order to introduce to the reader, in chapter 1 the charge transport theory through a semiconductor and metal junction (Schottky contact) and the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device are explained. Besides, the concept of variability and different sources of variability are also presented.
In the second chapter, advanced characterization techniques, such as, Conductive Atomic Force Microscopy (CAFM) and Kelvin Prove Force Microscopy (KPFM) used to obtain nanoscale information are described in detail. After that, the device simulator ATLAS, which is the Technology Computer-Aided Design (TCAD) simulator mainly used in this thesis, is explained. Here, the models and their limitations to simulate the electronic devices are discussed.
Third chapter is devoted to describe the impact of threading dislocation (TD) defects on the conduction through a schottky contact formed by a III-V semiconductor material (InGaAs) and a metal. Here, different conduction mechanisms, as Poole Frenkel (PF) and Thermionic Emission (TE), have been associated to the conduction through areas with TD and without TD, respectively, proving that III-V materials with high density of TD show higher leakage current.
In chapter four, the development and verification of a simulator called NAnoscale MAp Simulator (NAMAS) to generate automatically topography and density charge maps from inputs obtained with CAFM measurements (topography and current maps) of a given sample is explained. From the generated maps, the impact of the oxide thickness and the charge density fluctuations on MOSFET variability is studied.
In chapter five, the impact of interface traps in the gate oxide on device variability is analyzed. Firstly, the impact of interface discrete fixed charges on 65 nm technology MOSFET devices with different dimensions is studied (time-zero variability), where a deviation of Pelgrom's law is proved by experimental and TCAD simulation data. Next, the dynamic behavior of traps is analyzed by TCAD transient simulation in order to estimate their physical parameters from empiric parameters.
Chapter six is devoted to study the performance and power consumption trade-off in Ultra-thin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FDSOI) MOSFET when it is operated in near-threshold voltage. Besides, the impact of traps in gate oxide / channel and in buried oxide / channel interfaces on the performance and power consumption of the device is also analyzed.
Finally, in the last chapter of this thesis the more relevant conclusions are highlighted.
