Although silicon (Si) is used in most current commercial power semiconductor components, Si capabilities are insufficient for new energy conversion requirements. Some of its important limitations are related with power losses, operation temperature, radiation hardness and switching speed. Then, new semiconductor materials must be developed to face the future global energetic challenges, overcoming Si intrinsic limitations.
Silicon Carbide (SiC) is a proper wide bandgap (WBG) semiconductor with high critical electric field strength and a high saturation carrier’s drift velocity, which makes it able to sustain higher voltages with lower conduction losses. Furthermore, in a similar way to Si, SiC native oxide (SiO2) can be formed. However, a drawback of SiC MOSFETs is their poor oxide reliability and low channel mobility values attributed to a poor SiO2/SiC interface quality, with high density of interface traps (Dit) and near interface oxide traps (NIOTs). Nitridation processes, consisting in a nitric or nitrous oxide (NO, N2O) annealing is considered as the standard post oxidation annealing approach in 4H-SiC MOSFETs, being commonly used in commercial SiC power MOSFETs for reducing the Dit and NIOTs. However the nitridation interface passivation is not enough and, furthermore the limit of the improvement provided by nitridation has been reached.
This thesis is focused on 4H-SiC-based power devices, particularly, on one of the major issues in SiC technology: to find a suitable and reliable fabrication process that improves the gate oxide and SiO2/SiC interface quality and reliability. Regarding electrical performances, we will focus on two of the major challenges of this field: the improvement of the inversion channel mobility, and the gate oxide stability, in order to further reduce the on-resistance and enhance the gate oxide reliability. Both problems are related to the defects near the SiO2/SiC interface.
To meet these challenges and improve the current gate oxide quality state-of-the-art, several strategies were followed. We have worked on a newly interface passivation by oxynitridation methods combined with a boron diffusion treatment through the gate oxide. This novel approach allowed us to reach significantly high channel mobility values, up to 200 cm2/Vs. We also extensively studied the impact of the boron treatment parameters on the stability performances of our test structures, revealing some stability issues, especially at high temperature operation. In parallel, we have also worked on the improvement of the dielectric reliability by using a thin layer of a high-k material.
On the other hand, equally important, we studied the different fabrication issues found during the gate dielectric optimisation process. Taking into account the specific performances of our devices, we adapted the electrical and physical characterization processes required for a complete study of this kind of high mobility devices (for both, oxide and interface quality characterization, and final electrical MOSFET performance).
Finally, some studies which provide information about boron treatment impact on the oxide and interface traps, and about the global electrical behaviour of our devices are included in this thesis; concretely: i) A study on MOSFET mobility anisotropy, having into account different scattering mechanisms involved in channel carrier’s mobility.
ii) The effect of MOSFET channel dimensions in the obtained channel mobility.
iii) A comparison of B passivation effect on MOSFETs fabricated over 4H-SiC and 6H-SiC polytypes.
As a result, despite our new boron doping process is still not mature to be used in commercial devices, it allowed us to progress in the understanding of some of the phenomena taking place at the SiO2/SiC interface, in the way to properly characterise and interpret them, and in the way to further improve the MOS structure on SiC.
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