Neuromorphic deep convolutional neural network learning systems for FPGA in real time

• Autores: Ricardo Tapiador Morales
• Directores de la Tesis: Ángel Jiménez Fernández (dir. tes.), Alejandro Linares Barranco (dir. tes.), Gabriel Jiménez Moreno (dir. tes.)
• Lectura: En la Universidad de Sevilla ( España ) en 2019
• Idioma: inglés
• Número de páginas: 125
• Tribunal Calificador de la Tesis: Antonio Abad Civit Balcells (presid.), Francisco de Asís Gómez Rodríguez (secret.), Chiara Bartolozzi (voc.), Fernando Pérez Peña (voc.), Fernando Pardo Carpio (voc.)
• Programa de doctorado: Programa de Doctorado en Ingeniería Informática por la Universidad de Sevilla
• Materias:
  • Matemáticas
    • Ciencia de los ordenadores
      • Calculo digital
• Enlaces
  • Tesis en acceso abierto en: Idus
• Resumen

  • Deep Learning algorithms have become one of the best approaches for pattern recognition in several fields, including computer vision, speech recognition, natural language processing, and audio recognition, among others. In image vision, convolutional neural networks stand out, due to their relatively simple supervised training and their efficiency extracting features from a scene. Nowadays, there exist several implementations of convolutional neural networks accelerators that manage to perform these networks in real time. However, the number of operations and power consumption of these implementations can be reduced using a different processing paradigm as neuromorphic engineering. Neuromorphic engineering field studies the behavior of biological and inner systems of the human neural processing with the purpose of design analog, digital or mixed-signal systems to solve problems inspired in how human brain performs complex tasks, replicating the behavior and properties of biological neurons. Neuromorphic engineering tries to give an answer to how our brain is capable to learn and perform complex tasks with high efficiency under the paradigm of spike-based computation. This thesis explores both frame-based and spike-based processing paradigms for the development of hardware architectures for visual pattern recognition based on convolutional neural networks. In this work, two FPGA implementations of convolutional neural networks accelerator architectures for frame-based using OpenCL and SoC technologies are presented. Followed by a novel neuromorphic convolution processor for spike-based processing paradigm, which implements the same behaviour of leaky integrate-and-fire neuron model. Furthermore, it reads the data in rows being able to perform multiple layers in the same chip. Finally, a novel FPGA implementation of Hierarchy of Time Surfaces algorithm and a new memory model for spike-based systems are proposed.