Monolithic integration in standard cmos technologies of switching power converters for low power applications

• Autores: Gerard Villar Piqué
• Directores de la Tesis: Eduardo Alarcón (dir. tes.)
• Lectura: En la Universitat Politècnica de Catalunya (UPC) ( España ) en 2007
• Idioma: inglés
• Tribunal Calificador de la Tesis: Dragan Maksimovic (presid.), Francesc Guinjoan (secret.), José Antonio Cobos (voc.), Henk Jan Bergveld (voc.), Manuel Delgado Restituto (voc.)
• Materias:
  • Física
    • Electrónica
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• Resumen

  • The introduction of the thesis includes the work motivation and a brief review of the technological scenario that constitutes the framework in which the thesis is developed. In Chap. 2 the design space exploration is introduced and proposed to be applied on the switching power converters optimization. Indeed, a global procedure including several optimizations for each component design, which afterwards are included in the global design space exploration, is proposed. As an example, the same chapter covers the complete design of a Buck converter, where simplified models for each component are used. The chapter also presents a complete analytical model for the output voltage ripple evaluation, including the output capacitor ESR. Chapter 3 presents the detailed models and optimization procedures of the four different components that compose the Buck converter: inductor, capacitor, power drivers and power transistors. In all cases, a state of the art review is exposed, suggesting the requirements uncovered by the previous works, which justifies the proposed implementations and models. While only in some cases (capacitor and inductor) a particular microelectronic implementation is proposed, for any of them, models focusing the energy losses evaluation, and the occupied area, are provided. From the detailed models presented in the previous chapter, in Chap. 4 the complete design space exploration corresponding to the Buck converter is carried out. The obtained results from such procedure, that yield a DCM operated converter, are discussed and found to offer too low performance. Consequently, the search for a different converter topology more suitable to its fully monolithic integration is exposed. As a result, in Chap. 5, the implementation of an integrated 3-level converter is suggested and justified.