Power-efficient CMOS circuits for energy harvesting supplied IoT systems

• Autores: María Pilar Garde Luque
• Directores de la Tesis: Antonio López Martín (dir. tes.)
• Lectura: En la Universidad Pública de Navarra ( España ) en 2019
• Idioma: inglés
• Tribunal Calificador de la Tesis: Jaime Ramírez Angulo (presid.), Belen Teresa Calvo López (secret.), Ramón González Carvajal (voc.)
• Programa de doctorado: Programa de Doctorado en Tecnologías de las Comunicaciones, Bioingeniería y de las Energías Renovables por la Universidad Pública de Navarra
• Materias:
  • Física
    • Electrónica
      • Circuitos
      • Circuitos integrados
  • Ciencias tecnológicas
    • Tecnología electrónica
      • Diseño de circuitos
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• Resumen

  • In this thesis, innovative low voltage and low power techniques have been applied to implement novel analog circuits (mainly amplifiers). These circuits are suitable for energy autonomous devices such as those required in many Internet of Things (IoT) scenarios. The structure of the thesis is as follows: basic techniques for low voltage low power operation are proposed, at both cell and device level, followed by several novel basic building blocks using them and finally the achievement of new designs at subsystem level.

    At circuit level, different power efficient amplifiers are proposed in this work. They are obtained by combining different low voltage techniques. The main ones are the use of Quasi-Floating Gate (QFG) transistors some adaptive biasing techniques (the Flipped Voltage Follower, or FVF, and the Local Common-Mode Feedback, or LCMFB, among others). These schemes can be applied to single-ended or to fully differential amplifiers, leading to different topologies. The proposed circuits are compared with other relevant publications, showing a very competitive performance.

    At subsystem level, another low voltage technique, which is based in the use of floating voltage sources, is employed to design three blocks, two of them related to A/D conversion.

    The proposed circuits have been fabricated using different CMOS technologies (130 nm, 180 nm and 0.5 μm) and the corresponding measurement results are provided and analyzed to validate their operation. In addition, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.