Resumen de Networks-on-chip: from the optimization of traditional electronic nocs to the design of emerging optical nocs
As technology improves, memories and processors become faster, smaller, cheaper, and more energy-efficient, enabling computer architects to include more of them in a single chip. Now that Moore’s Law is reaching its limit, the replication of simple cores is being used to continue improving performance while minimizing fabrication costs. As a consequence, performance does not only face a bottleneck on computing power and memory access any more, but also on the communication of the chip elements. In this context, interconnection networks have emerged to replace buses as the prevailing solution to provide fast, cost-effective, and scalable communications. They are the key for the success of future digital systems, both chip multiprocessors composed of tens of identical cores and heterogeneous systems-on-chip. In the last decade, there has been an extensive research effort towards optimizing the networks-on-chip (NoCs) from low-level physical aspects all the way up to system-level and application-related issues, and NoCs have now reached a mature level of development with their integration as a fundamental component in many successful commercial products.
In this thesis, we start by analysing the state-of-the-art of electronic networks-on-chip and detect that, even though the fundamental purpose of the interconnect is to exchange information among processors and memories, it is often designed and optimized without taking those essential components into consideration. We revisit the comparison of several well-known topologies from a comprehensive point of view: running realistic applications on a detailed model of the processors, the caches, and the interconnect. This study identifies the dominant impact of the network latency and designates the concentrated mesh as the most cost-effective topology. Based on those observations, we propose a mechanism called Reactive Circuits that successfully leverages the information provided by the coherence protocol to reduce power and area, and improve performance. It uses the requests that travel across the network to dynamically build circuits for their replies, and is able to remove unnecessary buffer space and coherence messages.
As multiprocessors continue to scale, it is more challenging for these electronic networks-on-chip to meet their communication demands within the power budget. In consequence, a new technology is coming to the forefront with the objective of providing higher bandwidth and shorter latencies with reduced energy consumption. Although optical networks have already proved themselves useful for long distances and chip-to-chip communications, their establishment as on-chip networks still requires an intensive research effort, both in designing the new required mechanisms and devices, and in successfully proving their superiority against their electronic counterparts to compensate for the cost of migrating to the new technology.
In this work, we present an algorithm to automatically generate the communication matrices for optical rings with any number of nodes and minimum number of waveguides and wavelengths, and calculate their power consumption. We also introduce the first complete network interface architecture for optical networks and demonstrate it is responsible for most of the complexity of the optical NoC, both in latency and power. We then analyse the feasibility of the optical interconnect technology when integrated into industry-relevant objects: a chip multiprocessor and a general purpose multicore accelerator. By performing an accurate crossbenchmarking against an optimized electronic NoC, we determine that the optical network is better in latency and energy-per-bit, but still needs to be optimized in terms of power. With the objective of tackling that issue as well as adapting the optical networks to the virtualization paradigm frequent in multicore accelerators, we design the first algorithm to partition an optical network while minimizing the number of used wavelengths, thus reducing power.
