Arithmetic Soft-Core Accelerators

• Autores: Daniel Ramiro Humberto Calderón Rocabado
• Directores de la Tesis: K.G.W. Goossens (dir. tes.)
• Lectura: En la Delft University of Technology ( Países Bajos ) en 2007
• Idioma: inglés
• Número de páginas: 178
• Enlaces
  • Tesis en acceso abierto en: ce-publications.et.tudelft.nl (pdf)
• Resumen

  • In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten’s and two’s comple- ment notations. The main design goal is to collapse multiple complex arith- metic operations into a single, universal arithmetic unit, aiming at the highest possible reutilization of shared hardware resources. More specifically, we pro- pose an Arithmetic unit for collapsed Sum-of-Absolute Differences (SAD) and Multiplication operations (AUSM). This unit collapses various multi-operand addition based operations, such as SAD, universal notation multiplication, Multiply-Accumulate (MAC), fractional multiplication. Our AUSM design demonstrated high hardware reutilization level of up to 75%, yet its perfor- mance is comparable to the fastest related stand-alone designs supporting the individual operations. Another complex arithmetic operation, considered in this thesis is Matrix-Vector Multiplication. We collapsed fixed-point dense and sparse matrix-vector multiplication in one unit. It’s Xilinx Virtex II Pro im- plementation suggests up to 21GOPS on a xc2vp100-6 FPGA device. Further- more, in this thesis, we propose an arithmetic unit for universal addition, which supports addition/subtraction in binary and Binary Coded Decimal (BCD) rep- resentations in various sign notations. The hardware reutilization level for this unit was 40% and its performance was estimated to be more than 82MOPS.

    All considered units require massively parallel memory organizations, capa- ble of providing high data throughput. Therefore, in this thesis, we propose a high-performance address generator (AGEN) employing a modified version of the low-order interleaved memory access approach. Our experiments suggest that the AGEN can produce 8 × 32 − bit addresses every 6 ns. Overall, in this dissertation, we demonstrated a design approach, which allows collapsing of multiple arithmetic operations into performance efficient universal designs with high level of hardware reutilization among the implemented functions.