Periodo de publicación recogido
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Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
S. Abe, Masanori Hashimoto, Takao Onoye
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 91, Nº 12, 2008, págs. 3481-3487
Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori Hashimoto, J. Yamaguchi, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 90, Nº 12, 2007, págs. 2661-2668
Transistor Sizing of LCD Driver Circuit for Technology Migration
Masanori Hashimoto
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 90, Nº 12, 2007, págs. 2712-2717
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 90, Nº 4, 2007, págs. 724-731
Statistical Analysis of Clock Skew Variation in H-Tree Structure
Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3375-3381
Successive Pad Assignment for Minimizing Supply Voltage Drop
Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3429-3436
Effects of On-Chip Inductance on Power Distribution Grid
Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 12, 2005, págs. 3564-3572
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 88, Nº 4, 2005, págs. 885-891
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 87, Nº 12, 2004, págs. 3251-3257
Representative Frequency for Interconnect R(f)L(f)C Extraction
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 86, Nº 12, 2003, págs. 2942-2951
Crosstalk Noise Estimation for Generic RC Trees
Masanori Hashimoto, Masao Takahashi, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 86, Nº 12, 2003, págs. 2965-2973
Increase in Delay Uncertainty by Performance Optimization
Masanori Hashimoto
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 85, Nº 12, 2002, págs. 2799-2802
Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design
Masanori Hashimoto, Hidetoshi Onodera
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 84, Nº 11, 2001, págs. 2769-2777
A Perfomance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori Hashimoto
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 83, Nº 12, 2000, págs. 2558-2568
Multi-Cycle Path Detection Based on Statistical Static Timing Analysis
Masanori Hashimoto
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 83, Nº 12, 2000, págs. 2600-2607
A power and delay optimization method using input reordering in cell-based CMOS circuits
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru
IEICE transactions on fundamentals of electronics, communications and computer, ISSN 0916-8508, Vol. 82, Nº. 1, 1999, págs. 159-166
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