A visual simulation environment for MIPS based on VHDL

• J.M. Álvarez Llorente ^[1] ; N. Pavón Pulido ^[1] ; J. Ballesteros Rubio ^[2]
  1. [1] Universidad de Huelva

     Universidad de Huelva

     Huelva, España

     
  2. [2] Universidad de Extremadura

     Universidad de Extremadura

     Badajoz, España

     
• Localización: Computers and education in the 21st century / Manuel Ortega Cantero (ed. lit.), José Bravo Rodríguez (ed. lit.), 2000, ISBN 1-280-20019-7, págs. 55-63
• Idioma: inglés
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• Resumen

  • An application to perform a visual simulation of a machine based on MIPS is presented in this paper. The advantage of this system in relation to conventional simulators is that the simulation engine is the result of a real simulation under a VHDL development environment, so that hardware description can be modified and simulated in several ways to test and study its performance. So, it is possible to join the versatility of a commercial VHDL development tool with the simple handling of a graphic environment. In addition, an assembler language has been defined to write simple applications in order to test the simulated computer.