Design and simulation of hybrid SET-CMOS inverter using macro-model technique

• M.S. El Kazdir ^[1] ; M. Rzaizi ^[1] ; K. El Assali ^[1] ; D. Abouelaoualim ^[1]
  1. [1] Cadi Ayyad University

     Cadi Ayyad University

     Marrakech-Medina, Marruecos

     
• Localización: Revista Mexicana de Física, ISSN-e 0035-001X, Vol. 68, Nº. 6, 2022, págs. 1136-1139
• Idioma: inglés
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• Resumen

  • The single-electron transistor (SET) is one of the state-of-the-art devices that can offer high operating speed with ultra-low power consumption. The SET macro-modeling, can be used for the simulation of a SET-CMOS logic circuit. In this work, we develop a new hybrid, SET-CMOS logic inverter macro-model whose effect is very useful in VLSI circuits design. All simulations are performed using the SIM-SCAPE environment of MATLAB SIMULINK. This architecture has been realized by implementing the NMOS logic of the conventional inverter with a SET macro-model. The simulation results show that the hybrid structure offers better performance. Indeed, the designed circuit is able to operate at room temperature.