Towards integrating hardware Data Plane acceleration in Network Functions Virtualization

• Autores: David Franco Veiga, Asier Atutxa Imatz, Jorge Sasiain García, Eder Ollora, María Victoria Higuero Aperribay, Jasone Astorga Burgo, Eduardo Jacob Taquet
• Localización: JITEL 2021 Libro de Actas: XV Jornadas de Ingeniería Telemática, A Coruña 2021 / Víctor Carneiro (ed. lit.), Laura Victoria Vigoya Morales (ed. lit.), 2021, ISBN 978-84-09-35131-2, págs. 224-227
• Idioma: inglés
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• Resumen

  • This paper proposes a framework for integrating data plane (DP) acceleration within the Network Functions Virtualization (NFV) architecture. Data plane programming (DPP) proves to be beneficial for NFV environments, as it provides full packet forwarding flexibility through the use of self-designed algorithms. Additionally, DPP provides high-performance networking, as the DP can be configured to execute specific functions on dedicated hardware. We present an integration of the DP acceleration within the ETSI NFV architecture that leverages custom DP functions implemented in hardware switches using P4 language. Besides, Open- Stack and Kubernetes are used as Virtualized Infrastructure Managers (VIMs) and Open Source MANO (OSM) as the Management and Orchestration (MANO) element. Keywords—P4, NFV, data plane acceleration