Effective On-Chip Traffic Compression in Embedded Systems

• Autores: María Soler, Jose Flich Cardo
• Localización: Actas de las XXIV Jornadas de Paralelismo / coord. por Guillermo Botella, Alberto A. del Barrio García, 2013, ISBN 978-84-695-8330-2, págs. 228-233
• Idioma: inglés
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• Resumen

  • As technology advances, multiprocessorsystems-on-chip (MPSoCs) increase with the numberof components, relying on an efficient on-chip network(NoC). As the size of the system increases, NoC performanceand power consumption become a centralissue.In this paper we design compression strategies atthe NoC level reducing the number of transmittedflits and consequently the energy consumed. The providedmechanism relies on the abundance of memorydata blocks filled with zeros in the analysed applications.We provide a hardware implementation forboth compression and decompression at a generic networkinterface (NI). Results show the effectiveness ofthe compression and decompression mechanisms andthe low overhead they introduce. The percentage oftraffic reduced by the compression strategy (it is reducedby a factor of 3) justifies the added resources.