Enhanced built in self testing with reduced time and power consumption using minimum spanning tree

• Autores: H. Sribhuvaneshwari, K. Suthendran
• Localización: Sustainable development in engineering and technology, 2022, ISBN 978-84-124943-4-1, págs. 429-440
• Idioma: inglés
• Enlaces
  • Texto Completo Libro (pdf)
• Resumen

  • In today’s multi-million gate ICs, testing and verification are too expensive procedurein the design flow. For huge memory capacity, the testing process becomesmore complex and further it cannot be monitored & controlled by an external environmentor Automated Test Equipment (ATE). Therefore a built in mechanism isdesigned which allows a system or circuit to test by its own is called Built-In Self-Test(BIST), here patterns are formed using different algorithms, each algorithm is specificallyfocused to a particular type of circuitry or fault type. The main objective ofBIST is to find the defect with minimal power consumption, time and obtaining 100%fault coverage. In this article an enhanced BIST method is proposed for ResistiveRandom Access Memory (RRAM) using minimum spanning tree which results in welloptimized test complexity, time, power consumption with 100% fault coverage.