A study on various algorithms for global routing in VLSI
- Autores: Pandiaraj Kadarkarai, Sivakumar Pothiraj
- Localización: Sustainable development in engineering and technology, 2022, ISBN 978-84-124943-4-1, págs. 481-494
- Idioma: inglés
- Enlaces
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Resumen
The monstrous burden of VLSI circuits has driven global routing to a NP-completeone all through late years. With the appearance of 3D ICs, this drawback has becomefar more complicated. Thermal dissipation will increase in 3D ICs because of closeproximity of modules. several algorithms like minimum spanning trees, Steiner trees,integer linear programming are used for total wire length reduction. however, thesetechniques don't seem to be thermal and congestion aware and are of high quality.additionally, there's no benchmark out there for routing until currently covering3D routing area with each multiple metal layers and multiple device layers. 3D ICtechnology relies on multi-layer formation. TSVs (Through Si Vias) are accustomedproduce the interconnections between layers. during this work, a thermal and congestionaware formula are going to be developed to attenuate the amount of metallayers and thermal dissipation are often reduced by replacing the long metal layer interconnectsin 2d ICs with TSVs (Through Si Vias) in 3D ICs during which optimizationare often achieved by equalization design area and metal layer demand.
