This paper addresses the problem to completely carry out the implication of value assigned on (internal) nodes of a digital circuit. The most relevant case for this problem is in Automatic Test Pattern Generation since patterns are generated with a trial-and -error approach which heavily relies on implication. Ordering techniques and dynamic identification of useless elements are introduced to obtain a near-optimal solutions to the problem, the optimum being in general unreachable. The experiments carried out on a set of standard benchmark circuits support these considerations.
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