Identifying influencing factors on Branch Target Cache Memory performance

• A. Olivé ^[1] ; V. Viñals ^[1] ; C. Rodríguez ^[1]
  1. [1] Universitat Politècnica de Catalunya

     Universitat Politècnica de Catalunya

     Barcelona, España

     
• Localización: Mini and Microcomputers and their applications / Emilio Luque Fadón (ed. lit.), 1988, págs. 365-367
• Idioma: inglés
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• Resumen

  • In this paper, we study a particular organization for an instruction cache memory. This cache is tagged with the target addresses for taken branches and caches the target instruction as well as a fixed number of consecutive instruction bytes. Using traces from two 32-bit architectures (DEC VAX-11, Berkelsy RISCC-II), we find that a Branch Target Cache Memory (BTCM) in addition whit a burst-mode external memory and a prefetch mechanism can be very useful to supply instructions at the rate needed by teh processor.

    We define several hit ratios in order to isolate the factors that influence the global performance of a systems with a BTCM. Results of this measures for differents line sizes and number of entries are presented.