Resumen de Executing zero-delay branches with a Branch Target Buffer in a RISC processor

Teodor Jové Lagunas, Jordi Cortadella Fortuny

• The execution of branch instructions is one of the main reasons that impede a steady flow of instructions in a pipelined processor. In this paper we propose a new mechanism based on a Branch Target Buffer for executing branches whit zero-time delay cost in RISC architectures. The performance of this mechanism is compared with that obtained by the delayed- branch tecnique. An analytical estimation and simulation results about the performance are presented. Over 20% of performance improvement is obtained in comparison whit those mechanisms based on the delayed-branch technique.