Systolic architecture design for decoding convolutional codes using Viterbi algorithm

• Sadiq M. Sait ^[1] ; Ali F. Damati ^[1] ; Mushfiqur Rahman ^[1]
  1. [1] King Fahd University of Petroleum and Minerals

     King Fahd University of Petroleum and Minerals

     Arabia Saudí

     
• Localización: Mini and Microcomputers and their applications / Emilio Luque Fadón (ed. lit.), 1988, págs. 526-529
• Idioma: inglés
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• Resumen

  • The paper proposes a systolic algorithm for Viterbi decoding, and provides an architecture which is well-suited for VLSI implementation. The algorithm has been modeled in RTL (register transfer level), and simulated for functional correctness. The adventages of the algortihm are also mentioned.