Module level performance simulator for electrical and optical interconnects

• L. Guan ^[1] ; C. Pusarla ^[1] ; G. Halkias ^[1] ; A. Christou ^[1]
  1. [1] CALCE Electronic Packaging Research Center University of Maryland, USA
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 12, Nº 4, 1993, págs. 393-406
• Idioma: inglés
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• Resumen

  • As speed and complexity of electronic systems increase, the interconnect density has become the critical limitation to the performance of electrical systems. The performance of computing and switching systems can be increased by optimizing the interconnect density and throughput. At the board to board level, electrical interconnects at high speeds require a bulky and expensive backplane. At the chip to chip area, the allocation of interconnects limits the performance of the chips. Electrical lossy lines limit the maximum interconnect distance due to reflections, risetime degradation, increased delay, attenuation and cross talk . Optical interconnects present the possibility of solving the interconnect problems by potentially achieving a high bandwidth and high volume density of channels. At high data rates (greater than 1 Gb/s) several channels may operate with negligible mutual interference.