Signal delay for generally interconnected distributed structures

• Corneliu A. Marinov ^[1] ; Jukka Pekka Santanen ^[1]
  1. [1] Faculty of Electrotechnics, Polytechnical Institute of Bucharest, Rumanía
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 11, Nº 4, 1992, págs. 537-544
• Idioma: inglés
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• Resumen

  • A network composed by RC distributed parameter lines with resistively grounded nodes is considered. Upper and lower bounds for the transient voltages are inferred. The results are of interest for the signal delay evaluation in VLSI interconnections. A numerical example is presented.