Simulation of interface coupling effects in ultra-thin silicon on insulator MOSFET's

• A. Hassein-Bey ^[1] ; S. Cristoloveanu ^[1]
  1. [1] Laboratoire de Physique des Composants à Semiconducteurs (UA—CNRS), Francia
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 11, Nº 4, 1992, págs. 513-517
• Idioma: inglés
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• Resumen

  • Recent progress in silicon—on—insulator (SOI) technologies has made possible the fabrication of high quality ultra—thin film structures. Preliminary research has demonstrated the advantage of fully—depleted SOI MOSFET's in term of speed and improved resistance to hot carrier degradation. The specific dual‐gate configuration of SOI transistors is schematically presented in Fig. 1(a).