Mapping of internal distributions onto a lumped element network for CMOS latch-up simulation

• C. Werner ^[1] ; J. Harter ^[1] ; D. Takacs ^[1] ; A.W. Wieder ^[1]
  1. [1] Siemens AG, Research Laboratories, Alemania
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 2, Nº 4, 1983, págs. 195-206
• Idioma: inglés
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• Resumen

  • An efficient device simulation method is presented, which has been derived from mapping the results of a complete two‐dimensional (2‐D) analysis onto an equivalent lumped element network. The method is currently being used to predict latch‐up sensitivities of CMOS process design.