Memory disambiguation hardware: a Review

• Autores: Fernando Castro Rodríguez, Daniel Ángel Chaver Martínez, Luis Piñuel Moreno, Manuel Prieto Matías, Francisco Tirado Fernández
• Localización: Journal of Computer Science and Technology, ISSN-e 1666-6038, Vol. 8, Nº. 3, 2008 (Ejemplar dedicado a: Twenty-Fourth Issue), págs. 132-138
• Idioma: inglés
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• Resumen

  • One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.