Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology

• Autores: Erry Dwi Kurniawan, Hao Yang, Chia-Chou Lin, Yung-Chun Wu
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 83, 2018, págs. 254-259
• Idioma: inglés
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• Resumen

  • In this paper, we investigate the impact of fin-shape, dimension, and geometry of tapered FinFET with 5-nm node (N5) technology using TCAD simulation. Fixed gate length (LG) of 9nm, spacer length (LSP) of 7nm, and bottom fin-width (FWB) of 6nm were used. The other parameters, such as top fin-width (FWT) and fin-height (FH) were modulated to see the impact on the electrical characteristic and physical behaviors of the device. The simulation results show that increasing FH can enhance the saturation current (ISAT) effectively. However, the threshold voltage (VTH) will suffer so much. In addition, a higher FH means that a larger aspect ratio, thus it is not easy to fabricate in the manufacturing process. On the other hand, the saturation current can be improved by widening FWB. Nevertheless, it may not be a good choice because a wider FWB lets a larger cross-section device area for epitaxy source and drain. Tuning FWT may be the best choice to have a current gain. Additional 1nm FWT can enhance approximately 30% of the saturation current. Moreover, the VTH has no significant impact and it is good for source-drain epitaxy. By careful control of FH and FWT, the device performance can be predicted very well. As the results, Moore's law still can work even in N5 CMOS technology.