Study of synchronization test methods of NoC at multi‐clock domains

• Shu-yan Jiang ^[1] ; Gang Luo ^[2] ; Su Chen ^[1] ; Wen-han Zhao ^[1] ; Qi-zhong Zhou ^[1]
  1. [1] University of Electronic Science and Technology of China

     University of Electronic Science and Technology of China

     China

     
  2. [2] Chengdu Institute of Technology
• Localización: Compel: International journal for computation and mathematics in electrical and electronic engineering, ISSN 0332-1649, Vol. 32, Nº 2 (Special Issue: CAC 2010), 2013, págs. 504-515
• Idioma: inglés
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• Resumen

  • Purpose – The purpose of this paper is to introduce several synchronization test methods of Network‐on‐Chip (NoC) at multi‐clock domains by digital logic circuits.

    Design/methodology/approach – First, the authors gave the structure of NoC, the test methods for NoC in multi‐clock domains, including Built‐in Self Test (BIST) structure and the architecture of embedded core test. Then the authors approached four different synchronization structures: two‐level trigger, two kinds of lock methods, toggle and pulse synchronization methods. Based on the NoC work conditions, the authors built the experiment structures of different methods, and obtained the experiment results at high frequencies.

    Findings – From the experiments at high frequency, it can be seen that the methods of toggle and the pulse methods are prone to failed synchronization. Therefore, the lock method is more appropriate for NoC under multiple clock domains.

    Originality/value – In this paper, several synchronization test methods of NoC at multi‐clock domains are discussed and compared, and the best one determined.