Resumen de Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs
Igor Villalta, Unai Bidarte Peraita, Julen Gomez-Cornejo Barrena, Jesus Lazaro Sanz, Armando Astarloa Cuellar
Abstract Due to the continuous reduction of the transistor size in electronic devices, it is becoming more and more likely for an SEU (Single Event Upset) to provoke a flip on two or more memory cells in SRAM based FPGAs, which is called a MCU (Multiple Cell Upset). Fault injection in the configuration memory of these devices has been used for many years, in order to evaluate their reliability. Emulation of these injections using the bitstream file has always been a simple, fast and cheap solution. Most of the existent SEU emulation tools do not consider the injection of MCUs, and they do not discuss the implication MCUs have on the overall failure rate of the system. In this work, bitstream based SEU emulators are updated to consider MCUs. It is discussed the necessity of injecting faults on physically adjacent cells, in order to emulate appropriately the effect of MCUs. Adjacent MCU injection has been compared theoretically with an approach considering MCUs as bunches of independent SBUs, as it is done in other emulation platforms. A Zynq-based fault injection platform has been used, in order to apply this way of emulating MCUs and validate the proposal.
